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Searched +full:uniphier +full:- +full:gpio (Results 1 – 21 of 21) sorted by relevance

/linux/arch/arm/boot/dts/socionext/
H A Duniphier-ld4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-ld4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
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H A Duniphier-sld8.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-sld8";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
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H A Duniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
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H A Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
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H A Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
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H A Duniphier-ld4-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld4.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD4 Reference Board";
15 compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
18 stdout-path = "serial0:115200n8";
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H A Duniphier-sld8-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-sld8.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier sLD8 Reference Board";
15 compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
18 stdout-path = "serial0:115200n8";
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H A Duniphier-ld6b-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD6b Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld6b.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD6b Reference Board";
15 compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
18 stdout-path = "serial0:115200n8";
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H A Duniphier-pro4-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-pro4.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier Pro4 Reference Board";
15 compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
18 stdout-path = "serial0:115200n8";
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H A Duniphier-support-card.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Support Card (Expansion Board)
5 // Copyright (C) 2015-2017 Socionext Inc.
15 phy-mode = "mii";
16 reg-io-width = <4>;
17 interrupt-parent = <&gpio>;
23 clock-frequency = <12288000>;
24 reg-shift = <1>;
25 interrupt-parent = <&gpio>;
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
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H A Duniphier-ld11-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 Reference Board
8 /dts-v1/;
9 #include "uniphier-ld11.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD11 Reference Board";
15 compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
18 stdout-path = "serial0:115200n8";
53 &gpio {
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H A Duniphier-ld20-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld20.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD20 Reference Board";
15 compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
18 stdout-path = "serial0:115200n8";
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H A Duniphier-pxs3-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 Reference Board
8 /dts-v1/;
9 #include "uniphier-pxs3.dtsi"
10 #include "uniphier-support-card.dtsi"
13 model = "UniPhier PXs3 Reference Board";
14 compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
17 stdout-path = "serial0:115200n8";
70 &gpio {
71 xirq4-hog {
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/linux/Documentation/devicetree/bindings/gpio/
H A Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier GPIO controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
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/linux/drivers/gpio/
H A Dgpio-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/gpio/driver.h>
16 #include <dt-bindings/gpio/uniphier-gpio.h>
43 * Unfortunately, the GPIO port registers are not contiguous because in uniphier_gpio_bank_to_reg()
44 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. in uniphier_gpio_bank_to_reg()
65 spin_lock_irqsave(&priv->lock, flags); in uniphier_gpio_reg_update()
66 tmp = readl(priv->regs + reg); in uniphier_gpio_reg_update()
69 writel(tmp, priv->regs + reg); in uniphier_gpio_reg_update()
70 spin_unlock_irqrestore(&priv->lock, flags); in uniphier_gpio_reg_update()
107 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # GPIO infrastructure and drivers
10 bool "GPIO Support"
12 This enables GPIO support through the generic GPIO library.
14 one or more of the GPIO drivers below.
50 this symbol, but new drivers should use the generic gpio-regmap
54 bool "Debug GPIO calls"
57 Say Y here to add some extra checks and diagnostics to GPIO calls.
60 non-sleeping contexts. They can make bitbanged serial protocols
65 bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
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/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
90 tristate "GPIO reset controller"
94 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
97 If compiled as module, it will be called reset-gpio.
146 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
155 Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
231 Raspberry Pi 4's co-processor controls some of the board's HW
234 interfacing with RPi4's co-processor and model these firmware
272 - Altera SoCFPGAs
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
10 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
120 cores. This bus is for per-CPU tightly coupled devices such as the
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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