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/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
41 #define AR_IER 0x0024 /* Interrupt global enable register */
44 #define AR_TXCFG 0x0030 /* TX configuration register */
49 #define AR_TXNOFRM 0x004c /* TX no frame timeout register */
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_gen.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
[all …]
H A Dal_hal_serdes_internal_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
75 /* TX lane power state control */
94 /* TX lane word width */
[all …]
H A Dal_hal_serdes_hssp_internal_regs.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
74 /* TX lane power state control */
93 /* TX lane word width */
111 /* TX lane rate select */
[all …]
/freebsd/sys/dev/bfe/
H A Dif_bfereg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
41 #define BFE_PME 0x00001000 /* PHY Mode Enable */
42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
46 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
59 #define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */
71 #define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
79 #define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
86 #define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgereg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
55 #define VGE_TXCTL 0x07 /* TX control register */
81 #define VGE_TXHOSTERR 0x22 /* TX host error status */
86 #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
88 #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */
92 #define VGE_TXQTIMER 0x3E /* TX queue timer pend register */
[all …]
/freebsd/sys/dev/le/
H A Dlancereg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
[all …]
/freebsd/sys/dev/smc/
H A Dif_smcreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
42 #define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
43 #define TCR_NOCRC 0x0100 /* Disable/enable CRC */
45 #define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */
46 #define TCR_STP_SQET 0x1000 /* Stop TX on signal quality error */
52 #define EPHSR_TX_SUC 0x0001 /* Last TX was successful */
53 #define EPHSR_SNGLCOL 0x0002 /* Single collision on last TX */
54 #define EPHSR_MULCOL 0x0004 /* Multiple collisions on last TX */
[all …]
/freebsd/sys/dev/ic/
H A Dz8530.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
57 #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
61 #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
84 #define BES_TXU 0x40 /* Tx Underrun (EOM). */
88 #define BES_TXE 0x04 /* Tx Empty. */
93 #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
96 #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97 #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
98 #define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
[all …]
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
[all …]
/freebsd/sys/dev/cas/
H A Dif_casreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
53 #define CAS_BIM_LDEV_OEN 0x1020 /* BIM local device output enable */
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
88 #define CAS_INTR_TX_ALL 0x00000002 /* TX frames trans. to FIFO. */
89 #define CAS_INTR_TX_DONE 0x00000004 /* Any TX frame transferred. */
90 #define CAS_INTR_TX_TAG_ERR 0x00000008 /* TX FIFO tag corrupted. */
[all …]
/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
[all …]
/freebsd/share/man/man4/
H A Dena.41 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
66 The ENA devices enable high speed and low overhead network traffic
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
[all …]
/freebsd/sys/dev/e1000/
H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
[all …]
H A De1000_82575.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
46 * These entries are also used for MAC-based filtering.
93 #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */
178 #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
226 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
250 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
251 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
259 /* 1st & Last TSO-full iSCSI PDU*/
265 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
182 /** Tx to Rx VLAN ID selection type */
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
268 al_bool obay_enable; /**< stop tx when pause received */
278 * if prio_q_map[1][7] = 0xC, then TX queues 2
[all …]
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
309 struct al_eth_mac_10g_stats_v3_tx tx; member
428 /* [0x5c] SerDes TX FIFO control */
430 /* [0x60] SerDes TX FIFO status */
550 /* [0x4] TX ASYNC FIFO configuration */
552 /* [0x8] TX ASYNC FIFO configuration */
554 /* [0xc] TX ASYNC FIFO configuration */
556 /* [0x10] TX ASYNC FIFO configuration */
558 /* [0x14] TX ASYNC FIFO configuration */
[all …]
H A Dal_hal_eth_ec_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
72 /* [0x18] Enable modules operation (extended operations). */
214 /* [0x38] VLAN p-bits table address */
216 /* [0x3c] VLAN p-bits table data */
374 /* [0x0] Tx FIFO Wr configuration */
380 /* [0xc] Tx FIFO Rd configuration */
382 /* [0x10] Tx FIFO Rd configuration, checksum insertion */
[all …]
/freebsd/sys/dev/mwl/
H A Dmwlhal.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
39 #define MWL_MBSS_SUPPORT /* enable multi-bss support */
42 * Define total number of TX queues in the shared memory.
85 * Query whether multi-bss support is available/enabled.
114 int8_t maxTxPow; /* max tx power (dBm) */
132 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
138 bus_space_write_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
[all …]
/freebsd/sys/dev/igc/
H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dtestmode.h1 /* SPDX-License-Identifier: ISC */
13 * enum mt76_testmode_attr - testmode attributes inside NL80211_ATTR_TESTDATA
26 * @MT76_TM_ATTR_TX_LENGTH: packet tx mpdu length (u32)
27 * @MT76_TM_ATTR_TX_RATE_MODE: packet tx mode (u8, see &enum mt76_testmode_tx_mode)
28 * @MT76_TM_ATTR_TX_RATE_NSS: packet tx number of spatial streams (u8)
29 * @MT76_TM_ATTR_TX_RATE_IDX: packet tx rate/MCS index (u8)
30 * @MT76_TM_ATTR_TX_RATE_SGI: packet tx use short guard interval (u8)
31 * @MT76_TM_ATTR_TX_RATE_LDPC: packet tx enable LDPC (u8)
32 * @MT76_TM_ATTR_TX_RATE_STBC: packet tx enable STBC (u8)
33 * @MT76_TM_ATTR_TX_LTF: packet tx LTF, set 0 to 2 for 1x, 2x, and 4x LTF (u8)
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb_82599.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
41 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
62 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); in ixgbe_dcb_get_tc_stats_82599()
64 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc)); in ixgbe_dcb_get_tc_stats_82599()
65 stats->qbtc[tc] += in ixgbe_dcb_get_tc_stats_82599()
68 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); in ixgbe_dcb_get_tc_stats_82599()
70 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc)); in ixgbe_dcb_get_tc_stats_82599()
71 stats->qbrc[tc] += in ixgbe_dcb_get_tc_stats_82599()
75 stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc)); in ixgbe_dcb_get_tc_stats_82599()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dnvidia,tegra20-hsuart.txt4 - compatible : should be,
5 "nvidia,tegra20-hsuart" for Tegra20,
6 "nvidia,tegra30-hsuart" for Tegra30,
7 "nvidia,tegra186-hsuart" for Tegra186,
8 "nvidia,tegra194-hsuart" for Tegra194.
10 - reg: Should contain UART controller registers location and length.
11 - interrupts: Should contain UART controller interrupts.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets : Must contain an entry for each entry in reset-names.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,wcnss.txt6 - compatible:
11 - qcom,smd-channel:
18 - qcom,mmio:
20 Value type: <prop-encoded-array>
27 - firmware-name:
41 - compatible:
45 "qcom,wcnss-bt"
47 - local-bd-address:
55 - compatible:
59 "qcom,wcnss-wlan",
[all …]

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