Lines Matching +full:tx +full:- +full:enable
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
57 #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
61 #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
84 #define BES_TXU 0x40 /* Tx Underrun (EOM). */
88 #define BES_TXE 0x04 /* Tx Empty. */
93 #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
96 #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97 #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
98 #define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */
99 #define CMC_TC_BRG 0x10 /* Tx Clock from BRG */
100 #define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
101 #define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
102 #define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
103 #define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
104 #define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
105 #define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
106 #define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
109 #define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */
110 #define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */
114 #define CR_RSTTXI 0x28 /* Reset Tx. Int. */
115 #define CR_ENARXI 0x20 /* Enable Rx. Int. */
120 #define EFC_ERE 0x40 /* Extended Read Enable. */
126 #define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */
130 #define IC_TXU 0x40 /* Tx Underrun IE. */
134 #define IC_FIFO 0x04 /* SDLC FIFO Enable. */
136 #define IC_EF 0x01 /* Extended Feature Enable. */
139 #define IDT_WRE 0x80 /* Wait/DMA Request Enable. */
146 #define IDT_TIE 0x02 /* Tx Int. Enable. */
147 #define IDT_XIE 0x01 /* Ext. Int. Enable. */
151 #define IP_TIA 0x10 /* Tx. Int. ch. A. */
154 #define IP_TIB 0x02 /* Tx. Int. ch. B. */
180 #define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
181 #define MCB2_FM 0xc0 /* DPLL - FM mode. */
182 #define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
183 #define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
184 #define MCB2_OFF 0x60 /* DPLL - Disable. */
185 #define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
186 #define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
191 #define MCB2_BRGE 0x01 /* BRG enable. */
197 #define MIC_SIE 0x20 /* Software INTACK Enable. */
199 #define MIC_MIE 0x08 /* Master Interrupt Enable. */
211 #define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
212 #define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
216 #define MPM_SYNC 0x00 /* Sync Mode Enable. */
218 #define MPM_PE 0x01 /* Async mode: parity enable. */
225 #define RPC_AE 0x20 /* Auto Enable. */
227 #define RPC_CRC 0x08 /* CRC Enable. */
230 #define RPC_RXE 0x01 /* Receiver Enable */
249 #define TPC_TXE 0x08 /* Transmitter Enable. */
252 #define TPC_CRC 0x01 /* CRC Enable. */