Lines Matching +full:tx +full:- +full:enable
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
29 #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
129 #define IGC_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
132 /* Enable MAC address filtering */
134 /* Enable MNG packets to host memory */
144 #define IGC_RCTL_EN 0x00000002 /* enable */
146 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
147 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
148 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */
158 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
168 #define IGC_RCTL_VFE 0x00040000 /* vlan filter enable */
169 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
231 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
232 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
233 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
278 /* 1000/H is not supported, nor spec-compliant. */
316 #define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
320 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
324 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
332 #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
341 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
342 #define IGC_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
345 /* GPY211 - I225 defines */
426 /* Uncorrectable/correctable ECC Error counts and enable bits */
474 #define IGC_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
475 #define IGC_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
476 #define IGC_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
477 #define IGC_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
482 #define IGC_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
502 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
524 #define IGC_EIMS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
525 #define IGC_EIMS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
526 #define IGC_EIMS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
527 #define IGC_EIMS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
541 #define IGC_EICS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
542 #define IGC_EICS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
543 #define IGC_EICS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
544 #define IGC_EICS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
560 /* Enable the counting of descriptors still to be processed. */
604 /* Loop limit on how long we wait for auto-negotiation to complete */
619 #define IGC_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
634 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
635 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
644 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
681 #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */
682 #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */
683 #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */
685 #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */
687 #define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */
688 #define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */
695 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
700 #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
743 #define IGC_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
754 #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
786 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
787 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
792 #define IGC_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
818 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
823 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
852 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
853 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
864 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
865 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
877 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
878 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
903 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
917 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 /* NVM Commands - Microwire */
1034 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1042 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1132 #define M88IGC_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1229 #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1254 #define IGC_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1258 #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1260 * of EEE LPI Tx state
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out
1264 * of EEE LPI Tx state
1288 #define IGC_TXPB0S_SIZE_I225_MASK 0x0000003F /* Tx packet buffer 0 size */
1337 #define IGC_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1340 #define IGC_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1342 #define IGC_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1343 #define IGC_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */