Lines Matching +full:tx +full:- +full:enable
17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
262 #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
263 #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
264 #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
265 #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
266 #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
267 #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
270 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */
279 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
289 #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
306 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
310 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
312 #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
313 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
315 #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
320 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
323 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
324 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
325 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
327 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
330 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
336 #define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
339 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
340 #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
342 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
344 #define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */
345 #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */
346 #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */
351 #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
369 #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
380 #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */
383 #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */
384 #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */
385 #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
386 #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */
388 #define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */
389 #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */
390 #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
392 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
394 #define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */
395 #define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */
396 #define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */
397 #define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */
399 #define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */
400 #define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */
401 #define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */
402 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */
403 #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */
407 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
414 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
441 /* Special ISR registers (Yukon-2 only) */
450 * - completely empty (this is the RAP Block window)
466 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
467 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
499 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
502 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
504 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
525 * Bank 4 - 5
528 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
529 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
530 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
531 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
532 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
533 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
534 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
538 /* RSS key registers for Yukon-2 Family */
539 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
545 /* 0x0280 - 0x0292: MAC 2 */
550 * Bank 8 - 15
601 * Bank 16 - 23
624 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
630 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
631 #define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
632 #define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
633 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
642 /* 0x0c80 - 0x0cbf: MAC 2 */
643 /* 0x0cc0 - 0x0cff: reserved */
648 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
649 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
650 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
651 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
652 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
653 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
654 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
655 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
656 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
657 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
658 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
663 /* 0x0d80 - 0x0dbf: MAC 2 */
664 /* 0x0daa - 0x0dff: reserved */
678 /* Polling Unit Registers (Yukon-2 only) */
683 /* ASF Subsystem Registers (Yukon-2 only) */
700 /* Status BMU Registers (Yukon-2 only)*/
709 #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
711 /* FIFO Control/Status Registers (Yukon-2 only)*/
719 /* Level and ISR Timer Registers (Yukon-2 only)*/
724 #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
725 #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
726 #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
727 #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
734 #define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
735 #define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
748 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
750 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
757 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
758 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
772 * Bank 32 - 33
777 /* offset to configuration space on Yukon-2 */
786 #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
787 #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
788 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
789 #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */
790 #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */
791 #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */
792 #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */
793 #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */
794 #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */
795 #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */
809 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
811 #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
831 #define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */
866 #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
867 #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */
872 #define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */
873 #define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */
878 #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
879 #define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
898 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
899 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
900 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
901 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
902 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
903 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
904 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
905 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
906 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */
907 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */
909 #define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */
911 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
912 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
913 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
914 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
916 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
917 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
918 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
923 #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
925 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */
926 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */
928 #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */
929 #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */
930 #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */
932 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
942 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
953 /* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
954 /* Yukon-EC/FE */
957 /* Yukon-2 */
962 #define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */
993 #define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */
997 #define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */
1005 #define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */
1048 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
1065 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
1066 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
1067 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
1068 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
1071 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
1072 #define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */
1073 #define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */
1074 #define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */
1078 #define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */
1079 #define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */
1081 /* TXA_TEST 8 bit Tx Arbiter Test Register */
1082 #define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */
1083 #define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */
1084 #define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */
1085 #define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */
1086 #define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */
1087 #define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */
1089 /* TXA_STAT 8 bit Tx Arbiter Status Register */
1095 /* Rx BMU Control / Status Registers (Yukon-2) */
1099 #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
1101 #define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
1104 #define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
1106 #define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
1107 #define BMU_START BIT_8 /* Start Rx/Tx Queue */
1110 #define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
1114 #define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
1121 /* Tx BMU Control / Status Registers (Yukon-2) */
1123 #define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
1129 #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
1130 #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/
1132 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
1140 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
1175 #define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */
1177 #define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */
1187 /* Threshold values for Yukon-EC Ultra */
1191 #define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */
1195 #define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
1209 #define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
1210 #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
1216 /* Minimum RAM Buffer Tx Queue Size */
1250 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
1256 * Marvel-PHY Registers, indirect addressed over GMAC
1262 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
1264 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
1267 /* Marvel-specific registers */
1268 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
1269 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
1270 /* 0x0b - 0x0e: reserved */
1296 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
1298 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
1301 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
1306 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
1307 #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */
1308 #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */
1312 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
1314 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
1327 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1328 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1329 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1330 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1331 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1333 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1342 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1349 #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */
1350 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
1351 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1352 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
1353 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
1359 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1360 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1368 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1370 #define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */
1372 #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */
1377 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
1382 #define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */
1397 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
1399 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1402 #define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */
1410 #define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */
1411 #define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */
1413 #define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */
1433 #define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */
1446 #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */
1450 #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */
1466 #define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */
1467 #define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */
1475 #define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */
1479 #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */
1480 #define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */
1481 #define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */
1504 #define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */
1512 #define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */
1513 #define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */
1541 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */
1551 #define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */
1559 #define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */
1569 #define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */
1612 #define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */
1613 #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
1615 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1623 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
1625 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
1669 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1688 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */
1690 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1693 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1695 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1707 * MIB Counters base address definitions (low word) -
1737 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1739 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1741 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1743 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1745 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1747 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1771 (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */
1773 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1775 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1777 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1779 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1781 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1783 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1785 (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */
1787 (GM_MIB_CNT_BASE + 304) /* Tx Collision */
1789 (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */
1791 (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */
1793 (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */
1795 (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */
1797 (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */
1799 /*----------------------------------------------------------------------------*/
1813 #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */
1816 #define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */
1822 #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */
1825 #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */
1826 #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */
1827 #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */
1828 #define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */
1829 #define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */
1830 #define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */
1831 #define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */
1835 #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */
1837 #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */
1838 #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */
1839 #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
1846 #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */
1851 /* (Yukon-2 only) */
1857 #define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */
1858 #define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */
1859 #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */
1860 #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */
1867 /* (Yukon-2 only) */
1881 /* r/o on Yukon, r/w on Yukon-EC */
1882 #define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */
1883 #define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */
1884 #define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */
1885 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
1915 #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
1916 #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
1947 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1948 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
1949 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
1950 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
1951 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
1952 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
1953 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
1954 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
1957 #define RX_TRUNC_ON BIT_27 /* enable packet truncation */
1959 #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */
1963 #define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */
1965 #define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */
1982 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1983 #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
1984 #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
1985 #define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */
1987 #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */
1988 #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */
1993 #define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
1994 #define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
1995 #define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
2009 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
2014 #define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
2055 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2059 #define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
2067 #define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */
2068 #define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */
2081 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
2091 #define GPC_ENA_XC BIT_18 /* Enable MDI crossover */
2096 #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
2125 bus_write_4((sc)->msk_res[0], (reg), (val))
2127 bus_write_2((sc)->msk_res[0], (reg), (val))
2129 bus_write_1((sc)->msk_res[0], (reg), (val))
2132 bus_read_4((sc)->msk_res[0], (reg))
2134 bus_read_2((sc)->msk_res[0], (reg))
2136 bus_read_1((sc)->msk_res[0], (reg))
2139 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2141 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2143 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2146 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2148 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2150 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2153 CSR_READ_4((sc_if)->msk_softc, (reg))
2155 CSR_READ_2((sc_if)->msk_softc, (reg))
2157 CSR_READ_1((sc_if)->msk_softc, (reg))
2160 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))
2162 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
2164 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
2167 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
2188 /* Tx descriptor data structure */
2200 /* mask and shift value to get Tx async queue status for port 1 */
2204 /* mask and shift value to get Tx sync queue status for port 1 */
2208 /* mask and shift value to get Tx async queue status for port 2 */
2215 /* mask and shift value to get Tx sync queue status for port 2 */
2221 /* YUKON-2 bit values */
2227 /* YUKON-2 Control flags */
2244 /* YUKON-2 Rx/Tx opcodes defines */
2265 /* YUKON-2 STATUS opcodes defines */
2275 /* YUKON-2 SPECIAL opcodes defines */
2301 #define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */
2302 #define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */
2303 #define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */
2318 * number of RX buffers on platforms that support 64bit DMA. For TX
2319 * side, controller requires an additional OP_ADDR64 op code if a TX
2321 * Driver monitors high DMA address change in TX and inserts an
2323 * allocates 50% more total TX buffers on platforms that support 64bit
2357 #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2359 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
2360 #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
2412 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i))
2414 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2416 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2442 #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1)
2482 /* Tx stats. */
2543 #define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx)
2544 #define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx)
2545 #define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED)
2546 #define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc)
2547 #define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc)
2548 #define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc)
2550 #define MSK_USECS(sc, us) ((sc)->msk_clock * (us))
2577 uint32_t msk_txq; /* Tx. Async Queue offset */
2578 uint32_t msk_txsq; /* Tx. Syn Queue offset */