| /linux/drivers/clk/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
22 Choose Y here only if you build for this SoC.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
29 Choose Y here only if you build for this SoC.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
[all …]
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| /linux/drivers/clk/meson/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
56 bool "Meson8 SoC Clock controller support"
66 Support for the clock controller on AmLogic S802 (Meson8),
71 tristate "GXBB and GXL SoC clock controllers support"
83 Support for the clock controller on AmLogic S905 devices, aka gxbb.
87 tristate "AXG SoC clock controllers support"
98 Support for the clock controller on AmLogic A113D devices, aka axg.
102 tristate "Meson AXG Audio Clock Controller Driver"
111 Support for the audio clock controller on AmLogic A113D devices,
115 tristate "Amlogic A1 SoC PLL controller support"
[all …]
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| /linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
36 Say Y here if you want to enable PCI controller support on Amlogic
37 SoCs. The PCI controller on Amlogic is based on DesignWare hardware
38 and therefore the driver re-uses the DesignWare core functions to
[all …]
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| /linux/drivers/mmc/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MMC/SD host controller drivers
6 comment "MMC/SD/SDIO Host Controller Drivers"
18 tristate "Sunplus SP7021 MMC Controller"
37 bool "Qualcomm Data Mover for SD Card Controller"
41 This selects the Qualcomm Data Mover lite/local on SD Card controller.
48 bool "STMicroelectronics STM32 SDMMC Controller"
52 This selects the STMicroelectronics STM32 SDMMC host controller.
68 tristate "Secure Digital Host Controller Interface support"
71 This selects the generic Secure Digital Host Controller Interface.
[all …]
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| /linux/drivers/clk/starfive/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 Say yes here to support the clock controller on the StarFive JH7100
13 SoC.
22 SoC.
29 Say yes here to support the PLL clock controller on the
30 StarFive JH7110 SoC.
41 Say yes here to support the system clock controller on the
42 StarFive JH7110 SoC.
45 tristate "StarFive JH7110 always-on clock support"
49 Say yes here to support the always-on clock controller on the
[all …]
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| /linux/drivers/reset/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
12 via GPIOs or SoC-internal reset controller modules.
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
39 bool "BCM6345 Reset Controller"
43 This enables the reset controller driver for BCM6345 SoCs.
50 This enables the reset controller driver for Marvell Berlin SoCs.
[all …]
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| /linux/Documentation/devicetree/bindings/soc/litex/ |
| H A D | litex,soc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: LiteX SoC Controller driver
11 This is the SoC Controller driver for the LiteX SoC Builder.
17 - Karol Gugala <kgugala@antmicro.com>
18 - Mateusz Holenko <mholenko@antmicro.com>
22 const: litex,soc-controller
28 - compatible
[all …]
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| /linux/Documentation/devicetree/bindings/edac/ |
| H A D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
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| /linux/drivers/pinctrl/spear/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
26 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
32 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
38 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
44 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
50 bool "SPEAr SoC PLGPIO Controller"
54 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
|
| /linux/drivers/pinctrl/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
53 tristate "Apple SoC GPIO pin controller driver"
62 This is the driver for the GPIO controller found on Apple ARM SoCs,
66 will be called pinctrl-apple-gpio.
69 bool "Axis ARTPEC-6 pin controller driver"
74 This is the driver for the Axis ARTPEC-6 pin controller. This driver
77 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
86 functionality. This driver supports the pinmux, push-pull and
114 controller available on sama5d2 SoC.
117 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
[all …]
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| /linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "PCI controller drivers"
7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
14 controller is part of the South Bridge of the Marvel Armada
15 3700 SoC.
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
30 This MSI driver supports Altera MSI to GIC controller IP.
38 tristate "Apple PCIe controller"
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
[all …]
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
|
| H A D | brcm,iproc-gpio.txt | 1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
[all …]
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| /linux/drivers/pinctrl/sophgo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Sophgo SoC PINCTRL drivers
13 tristate "Sophgo CV1800B SoC Pinctrl driver"
18 Say Y to select the pinctrl driver for CV1800B SoC.
19 This pin controller allows selecting the mux function for
21 pinctrl-cv1800b.
24 tristate "Sophgo CV1812H SoC Pinctrl driver"
29 Say Y to select the pinctrl driver for CV1812H SoC.
30 This pin controller allows selecting the mux function for
32 pinctrl-cv1812h.
[all …]
|
| /linux/drivers/usb/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # USB Host Controller Drivers
5 comment "USB Host Controller Drivers"
11 The Cypress C67x00 (EZ-Host/EZ-OTG) chips are dual-role
14 Enable this option to support this chip in host controller mode.
24 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
25 "SuperSpeed" host controller hardware.
28 module will be called xhci-hcd.
46 tristate "Support for additional Renesas xHCI controller with firmware"
49 Say 'Y' to enable the support for the Renesas xHCI controller with
[all …]
|
| /linux/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
19 tristate "Denali NAND controller on Intel Moorestown"
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
32 controller as a DT device.
35 tristate "Amstrad E3 NAND controller"
42 tristate "OMAP2, OMAP3, OMAP4 and Keystone NAND controller"
69 This enables the driver for the NAND flash controller on the
70 AMD/Alchemy 1550 SOC.
[all …]
|
| /linux/drivers/clk/sophgo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for SOPHGO SoC family.
5 tristate "Support for the Sophgo CV1800 series SoCs clock controller"
8 This driver supports clock controller of Sophgo CV18XX series SoC.
11 IPs of CV18XX series SoC
17 This driver supports the PLL clock controller on the
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
32 tristate "Sophgo SG2042 RP subsystem clock controller support"
36 controller on the Sophgo SG2042 SoC.
|
| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
[all …]
|
| /linux/drivers/irqchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
94 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
134 tristate "Broadcom STB generic L2 interrupt controller driver"
175 Enable support for the LAN966x Outbound Interrupt Controller.
176 This controller is present on the Microchip LAN966x PCI device and
180 will be called irq-lan966x-oic.
221 bool "J-Core integrated AIC" if COMPILE_TEST
[all …]
|
| /linux/drivers/mailbox/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
15 Say Y here if you want to build the ARM MHU controller driver.
16 The controller has 3 mailbox channels, the last of which can be
23 Say Y here if you want to build the ARM MHUv2 controller driver,
32 Say Y here if you want to build the ARM MHUv3 controller driver,
37 will be discovered and possibly managed at probe-time.
51 controller driver.
52 The controller has a maximum of 3 mailbox channels, the last of
71 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
[all …]
|
| /linux/drivers/spi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
16 eeprom and flash memory, codecs and various other controller
17 chips, analog to digital (and d-to-a) converters, and more.
33 sysfs, and debugfs support in SPI controller and protocol drivers.
44 If your system has an master-capable SPI controller (which
46 controller and the protocol drivers for the SPI slave chips
56 by providing a high-level interface to send memory-like commands.
58 comment "SPI Master Controller Drivers"
[all …]
|
| /linux/drivers/pinctrl/samsung/ |
| H A D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
90 * Samsung GPIO controller groups all the available pins into banks. The pins
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
[all …]
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | realtek,rtl-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL SoC interrupt controller
10 Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
13 All connected input lines from SoC peripherals can be masked individually,
18 - Birger Koblitz <mail@birger-koblitz.de>
19 - Bert Vermeulen <bert@biot.com>
20 - John Crispin <john@phrozen.org>
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/socionext/ |
| H A D | socionext,uniphier-soc-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
[all …]
|