| /linux/drivers/clk/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
22 Choose Y here only if you build for this SoC.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
29 Choose Y here only if you build for this SoC.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
[all …]
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| /linux/drivers/clk/sophgo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for SOPHGO SoC family.
5 tristate "Support for the Sophgo CV1800 series SoCs clock controller"
8 This driver supports clock controller of Sophgo CV18XX series SoC.
11 IPs of CV18XX series SoC
17 This driver supports the PLL clock controller on the
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
32 tristate "Sophgo SG2042 RP subsystem clock controller support"
36 controller on the Sophgo SG2042 SoC.
[all …]
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| /linux/drivers/clk/meson/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
54 bool "Meson8 SoC Clock controller support"
64 Support for the clock controller on AmLogic S802 (Meson8),
69 tristate "GXBB and GXL SoC clock controllers support"
81 Support for the clock controller on AmLogic S905 devices, aka gxbb.
85 tristate "AXG SoC clock controllers support"
96 Support for the clock controller on AmLogic A113D devices, aka axg.
100 tristate "Meson AXG Audio Clock Controller Driver"
110 Support for the audio clock controller on AmLogic A113D devices,
114 tristate "Amlogic A1 SoC PLL controller support"
[all …]
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| /linux/drivers/reset/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
12 via GPIOs or SoC-internal reset controller modules.
30 This enables the reset controller driver for AST2700.
36 This enables the ATH79 reset controller driver that supports the
37 AR71xx SoC reset controller.
43 This enables the reset controller driver for AXS10x.
46 bool "BCM6345 Reset Controller"
50 This enables the reset controller driver for BCM6345 SoCs.
[all …]
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| /linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
14 Say Y here to enable debugfs entries for the PCIe controller. These
15 entries provide various debug features related to the controller and
30 bool "Amazon Annapurna Labs PCIe controller"
37 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
39 required only for DT-based platforms. ACPI platforms with the
40 Annapurna Labs PCIe controller don't need to enable this.
43 bool "AMD MDB Versal2 PCIe controller"
48 Say Y here if you want to enable PCIe controller support on AMD
[all …]
|
| /linux/drivers/clk/starfive/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 Say yes here to support the clock controller on the StarFive JH7100
13 SoC.
22 SoC.
29 Say yes here to support the PLL clock controller on the
30 StarFive JH7110 SoC.
41 Say yes here to support the system clock controller on the
42 StarFive JH7110 SoC.
45 tristate "StarFive JH7110 always-on clock support"
49 Say yes here to support the always-on clock controller on the
[all …]
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| /linux/Documentation/devicetree/bindings/soc/litex/ |
| H A D | litex,soc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: LiteX SoC Controller driver
11 This is the SoC Controller driver for the LiteX SoC Builder.
17 - Karol Gugala <kgugala@antmicro.com>
18 - Mateusz Holenko <mholenko@antmicro.com>
22 const: litex,soc-controller
28 - compatible
[all …]
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| /linux/drivers/pinctrl/spear/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
26 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
32 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
38 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
44 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
50 bool "SPEAr SoC PLGPIO Controller"
54 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
|
| /linux/Documentation/devicetree/bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
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| /linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "PCI controller drivers"
11 tristate "Aardvark PCIe controller"
18 Add support for Aardvark 64bit PCIe Host Controller. This
19 controller is part of the South Bridge of the Marvel Armada
20 3700 SoC.
23 tristate "Altera PCIe controller"
26 Say Y here if you want to enable PCIe controller support on Altera
36 This MSI driver supports Altera MSI to GIC controller IP.
44 tristate "Apple PCIe controller"
[all …]
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | realtek,rtl-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL SoC interrupt controller
10 Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
13 All connected input lines from SoC peripherals can be masked individually,
18 - Birger Koblitz <mail@birger-koblitz.de>
19 - Bert Vermeulen <bert@biot.com>
20 - John Crispin <john@phrozen.org>
[all …]
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| /linux/Documentation/devicetree/bindings/soc/socionext/ |
| H A D | socionext,uniphier-soc-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
[all …]
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| /linux/drivers/dma/stm32/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 Enable support for the on-chip DMA controller on STMicroelectronics
14 If you have a board based on STM32 SoC with such DMA controller
21 Enable support for the on-chip DMA multiplexer on STMicroelectronics
23 If you have a board based on STM32 SoC with such DMA multiplexer
32 Enable support for the on-chip MDMA controller on STMicroelectronics
34 If you have a board based on STM32 SoC with such DMA controller
42 Enable support for the on-chip DMA3 controller on STMicroelectronics
44 If you have a board based on STM32 SoC with such DMA3 controller
|
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
2 Mobile Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
20 /* Mellanox Bluefield SoC MMC */
[all …]
|
| H A D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
[all …]
|
| /linux/drivers/soc/loongson/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
3 # Loongson-2 series SoC drivers
7 tristate "Loongson-2 SoC Global UtiliTieS (GUTS) register block"
13 and PCIE, configuration of memory controller, rtc controller, lio
14 controller, and clock control. This patch adds a driver to manage
15 and access global utilities block for LoongArch architecture Loongson-2
16 SoCs. Initially only reading SVR and registering soc device are
21 bool "Loongson-2 SoC Power Management Controller Driver"
25 The Loongson-2's power management controller was ACPI, supports ACPI
27 Disk), ACPI S5 (Soft Shutdown) and supports multiple wake-up methods
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | sci-pm-domain.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI generic power domain
10 - Nishanth Menon <nm@ti.com>
13 - $ref: /schemas/power/power-domain.yaml#
16 Some TI SoCs contain a system controller (like the Power Management Micro
17 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
18 the state of the various hardware modules present on the SoC. Communication
[all …]
|
| /linux/drivers/memory/tegra/ |
| H A D | mc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
20 #include <soc/tegra/fuse.h>
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
[all …]
|
| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
|
| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | keystone-reset.txt | 3 This node is intended to allow SoC reset in case of software reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
17 access pll controller registers and the offset to use
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
33 begins from 0 to 3, as keystone can contain up to 4 SoC
[all …]
|
| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
17 registers and for its data input/output buffer. On some SoCs, this controller
[all …]
|
| /linux/drivers/phy/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Exynos SoC series Display Port PHY driver"
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
29 Enable PCIe PHY support for Exynos SoC series.
30 This driver provides PHY interface for Exynos PCIe controller.
33 tristate "Exynos SoC series UFS PHY driver"
38 Enable this to support the Samsung Exynos SoC UFS PHY driver for
40 controller to do PHY related programming.
43 tristate "S5P/Exynos SoC series USB 2.0 PHY driver"
[all …]
|
| /linux/drivers/ata/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
24 that "speaks" the ATA protocol, also called ATA controller),
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
78 from the ACPI BIOS and write them to the disk controller.
107 comment "Controllers with non-SFF native interface"
125 for chipsets / "South Bridges" supporting low-power modes. Such
128 - Partial: The Phy logic is powered but is in a reduced power
[all …]
|
| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | dcsr.txt | 21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
[all …]
|