1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 27b5c5720SJerome Brunetmenu "Clock support for Amlogic platforms" 37b5c5720SJerome Brunet depends on ARCH_MESON || COMPILE_TEST 47b5c5720SJerome Brunet 5889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_REGMAP 6889c2b7eSJerome Brunet tristate 7ea11dda9SJerome Brunet select REGMAP 821ed19d1SJerome Brunet select MFD_SYSCON 9ea11dda9SJerome Brunet 10889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_DUALDIV 11889c2b7eSJerome Brunet tristate 12889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 13889c2b7eSJerome Brunet 14889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_MPLL 15889c2b7eSJerome Brunet tristate 16889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 17889c2b7eSJerome Brunet 18889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_PHASE 19889c2b7eSJerome Brunet tristate 20889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 21889c2b7eSJerome Brunet 22889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_PLL 23889c2b7eSJerome Brunet tristate 24889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 25889c2b7eSJerome Brunet 26889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_SCLK_DIV 27889c2b7eSJerome Brunet tristate 28889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 29889c2b7eSJerome Brunet 30889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_VID_PLL_DIV 31889c2b7eSJerome Brunet tristate 32889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 33889c2b7eSJerome Brunet 34bb5aa085SNeil Armstrongconfig COMMON_CLK_MESON_VCLK 35bb5aa085SNeil Armstrong tristate 36bb5aa085SNeil Armstrong select COMMON_CLK_MESON_REGMAP 37bb5aa085SNeil Armstrong 38230b6f3aSNeil Armstrongconfig COMMON_CLK_MESON_CLKC_UTILS 39*e256a660SJerome Brunet select REGMAP 40*e256a660SJerome Brunet select MFD_SYSCON 41230b6f3aSNeil Armstrong tristate 42230b6f3aSNeil Armstrong 43889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_AO_CLKC 44889c2b7eSJerome Brunet tristate 45889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 467e1723fdSNeil Armstrong select COMMON_CLK_MESON_CLKC_UTILS 47889c2b7eSJerome Brunet select RESET_CONTROLLER 48889c2b7eSJerome Brunet 4926d34431SNeil Armstrongconfig COMMON_CLK_MESON_CPU_DYNDIV 5026d34431SNeil Armstrong tristate 5126d34431SNeil Armstrong select COMMON_CLK_MESON_REGMAP 5226d34431SNeil Armstrong 53cb7c47d7SMichael Turquetteconfig COMMON_CLK_MESON8B 547b5c5720SJerome Brunet bool "Meson8 SoC Clock controller support" 557b5c5720SJerome Brunet depends on ARM 560afce85eSKrzysztof Kozlowski default ARCH_MESON 57889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 585e4e4804SNeil Armstrong select COMMON_CLK_MESON_CLKC_UTILS 59889c2b7eSJerome Brunet select COMMON_CLK_MESON_MPLL 60889c2b7eSJerome Brunet select COMMON_CLK_MESON_PLL 61889c2b7eSJerome Brunet select MFD_SYSCON 6218962172SMartin Blumenstingl select RESET_CONTROLLER 63cb7c47d7SMichael Turquette help 64855f06a1SMartin Blumenstingl Support for the clock controller on AmLogic S802 (Meson8), 65855f06a1SMartin Blumenstingl S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you 66855f06a1SMartin Blumenstingl want peripherals and CPU frequency scaling to work. 67738f66d3SMichael Turquette 68738f66d3SMichael Turquetteconfig COMMON_CLK_GXBB 6920425f63SKevin Hilman tristate "GXBB and GXL SoC clock controllers support" 707b5c5720SJerome Brunet depends on ARM64 710afce85eSKrzysztof Kozlowski default ARCH_MESON 72889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 73*e256a660SJerome Brunet select COMMON_CLK_MESON_CLKC_UTILS 74889c2b7eSJerome Brunet select COMMON_CLK_MESON_DUALDIV 75889c2b7eSJerome Brunet select COMMON_CLK_MESON_VID_PLL_DIV 76889c2b7eSJerome Brunet select COMMON_CLK_MESON_MPLL 77889c2b7eSJerome Brunet select COMMON_CLK_MESON_PLL 78889c2b7eSJerome Brunet select COMMON_CLK_MESON_AO_CLKC 794162dd5bSJerome Brunet select MFD_SYSCON 80738f66d3SMichael Turquette help 81738f66d3SMichael Turquette Support for the clock controller on AmLogic S905 devices, aka gxbb. 82738f66d3SMichael Turquette Say Y if you want peripherals and CPU frequency scaling to work. 8378b4af31SQiufang Dai 8478b4af31SQiufang Daiconfig COMMON_CLK_AXG 8520425f63SKevin Hilman tristate "AXG SoC clock controllers support" 867b5c5720SJerome Brunet depends on ARM64 870afce85eSKrzysztof Kozlowski default ARCH_MESON 88889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 89*e256a660SJerome Brunet select COMMON_CLK_MESON_CLKC_UTILS 90889c2b7eSJerome Brunet select COMMON_CLK_MESON_DUALDIV 91889c2b7eSJerome Brunet select COMMON_CLK_MESON_MPLL 92889c2b7eSJerome Brunet select COMMON_CLK_MESON_PLL 93889c2b7eSJerome Brunet select COMMON_CLK_MESON_AO_CLKC 944162dd5bSJerome Brunet select MFD_SYSCON 9578b4af31SQiufang Dai help 9678b4af31SQiufang Dai Support for the clock controller on AmLogic A113D devices, aka axg. 9778b4af31SQiufang Dai Say Y if you want peripherals and CPU frequency scaling to work. 981cd50181SJerome Brunet 991cd50181SJerome Brunetconfig COMMON_CLK_AXG_AUDIO 1001cd50181SJerome Brunet tristate "Meson AXG Audio Clock Controller Driver" 1017b5c5720SJerome Brunet depends on ARM64 102889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 103889c2b7eSJerome Brunet select COMMON_CLK_MESON_PHASE 104889c2b7eSJerome Brunet select COMMON_CLK_MESON_SCLK_DIV 10505d3b7c6SNeil Armstrong select COMMON_CLK_MESON_CLKC_UTILS 106cb78ba76SJerome Brunet select REGMAP_MMIO 107301b96e0SJerome Brunet select AUXILIARY_BUS 108301b96e0SJerome Brunet imply RESET_MESON_AUX 1091cd50181SJerome Brunet help 1101cd50181SJerome Brunet Support for the audio clock controller on AmLogic A113D devices, 1111cd50181SJerome Brunet aka axg, Say Y if you want audio subsystem to work. 112085a4ea9SJian Hu 11328f3be51SDmitry Rokosovconfig COMMON_CLK_A1_PLL 11428f3be51SDmitry Rokosov tristate "Amlogic A1 SoC PLL controller support" 11528f3be51SDmitry Rokosov depends on ARM64 11628f3be51SDmitry Rokosov select COMMON_CLK_MESON_REGMAP 117c3f2801bSNeil Armstrong select COMMON_CLK_MESON_CLKC_UTILS 11828f3be51SDmitry Rokosov select COMMON_CLK_MESON_PLL 11928f3be51SDmitry Rokosov help 12028f3be51SDmitry Rokosov Support for the PLL clock controller on Amlogic A113L based 12128f3be51SDmitry Rokosov device, A1 SoC Family. Say Y if you want A1 PLL clock controller 12228f3be51SDmitry Rokosov to work. 12328f3be51SDmitry Rokosov 12484af9144SDmitry Rokosovconfig COMMON_CLK_A1_PERIPHERALS 12584af9144SDmitry Rokosov tristate "Amlogic A1 SoC Peripherals clock controller support" 12684af9144SDmitry Rokosov depends on ARM64 12784af9144SDmitry Rokosov select COMMON_CLK_MESON_DUALDIV 12884af9144SDmitry Rokosov select COMMON_CLK_MESON_REGMAP 129c3f2801bSNeil Armstrong select COMMON_CLK_MESON_CLKC_UTILS 13084af9144SDmitry Rokosov help 13184af9144SDmitry Rokosov Support for the Peripherals clock controller on Amlogic A113L based 13284af9144SDmitry Rokosov device, A1 SoC Family. Say Y if you want A1 Peripherals clock 13384af9144SDmitry Rokosov controller to work. 13484af9144SDmitry Rokosov 1358a9a129dSXianwei Zhaoconfig COMMON_CLK_C3_PLL 1368a9a129dSXianwei Zhao tristate "Amlogic C3 PLL clock controller" 1378a9a129dSXianwei Zhao depends on ARM64 1380afce85eSKrzysztof Kozlowski default ARCH_MESON 1398a9a129dSXianwei Zhao select COMMON_CLK_MESON_REGMAP 1408a9a129dSXianwei Zhao select COMMON_CLK_MESON_PLL 1418a9a129dSXianwei Zhao select COMMON_CLK_MESON_CLKC_UTILS 1428a9a129dSXianwei Zhao imply COMMON_CLK_SCMI 1438a9a129dSXianwei Zhao help 1448a9a129dSXianwei Zhao Support for the PLL clock controller on Amlogic C302X and C308L devices, 1458a9a129dSXianwei Zhao AKA C3. Say Y if you want the board to work, because PLLs are the parent 1468a9a129dSXianwei Zhao of most peripherals. 1478a9a129dSXianwei Zhao 148f06ac3edSXianwei Zhaoconfig COMMON_CLK_C3_PERIPHERALS 149f06ac3edSXianwei Zhao tristate "Amlogic C3 peripherals clock controller" 150f06ac3edSXianwei Zhao depends on ARM64 1510afce85eSKrzysztof Kozlowski default ARCH_MESON 152f06ac3edSXianwei Zhao select COMMON_CLK_MESON_REGMAP 153f06ac3edSXianwei Zhao select COMMON_CLK_MESON_DUALDIV 154f06ac3edSXianwei Zhao select COMMON_CLK_MESON_CLKC_UTILS 155f06ac3edSXianwei Zhao imply COMMON_CLK_SCMI 156f06ac3edSXianwei Zhao imply COMMON_CLK_C3_PLL 157f06ac3edSXianwei Zhao help 158f06ac3edSXianwei Zhao Support for the Peripherals clock controller on Amlogic C302X and 159f06ac3edSXianwei Zhao C308L devices, AKA C3. Say Y if you want the peripherals clock to 160f06ac3edSXianwei Zhao work. 161f06ac3edSXianwei Zhao 162085a4ea9SJian Huconfig COMMON_CLK_G12A 16320425f63SKevin Hilman tristate "G12 and SM1 SoC clock controllers support" 1647b5c5720SJerome Brunet depends on ARM64 1650afce85eSKrzysztof Kozlowski default ARCH_MESON 166085a4ea9SJian Hu select COMMON_CLK_MESON_REGMAP 167*e256a660SJerome Brunet select COMMON_CLK_MESON_CLKC_UTILS 168042f01bbSNeil Armstrong select COMMON_CLK_MESON_DUALDIV 169085a4ea9SJian Hu select COMMON_CLK_MESON_MPLL 170085a4ea9SJian Hu select COMMON_CLK_MESON_PLL 171042f01bbSNeil Armstrong select COMMON_CLK_MESON_AO_CLKC 17226d34431SNeil Armstrong select COMMON_CLK_MESON_CPU_DYNDIV 173bae69bfaSKevin Hilman select COMMON_CLK_MESON_VID_PLL_DIV 174b70cb1a2SNeil Armstrong select COMMON_CLK_MESON_VCLK 175085a4ea9SJian Hu select MFD_SYSCON 176085a4ea9SJian Hu help 177085a4ea9SJian Hu Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 178085a4ea9SJian Hu devices, aka g12a. Say Y if you want peripherals to work. 179e787c9c5SYu Tu 180e787c9c5SYu Tuconfig COMMON_CLK_S4_PLL 181e787c9c5SYu Tu tristate "S4 SoC PLL clock controllers support" 182e787c9c5SYu Tu depends on ARM64 1830afce85eSKrzysztof Kozlowski default ARCH_MESON 18498408df6SArnd Bergmann select COMMON_CLK_MESON_CLKC_UTILS 185e787c9c5SYu Tu select COMMON_CLK_MESON_MPLL 186e787c9c5SYu Tu select COMMON_CLK_MESON_PLL 187e787c9c5SYu Tu select COMMON_CLK_MESON_REGMAP 188e787c9c5SYu Tu help 189e787c9c5SYu Tu Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devices, 190e787c9c5SYu Tu AKA S4. Say Y if you want the board to work, because PLLs are the parent of 191e787c9c5SYu Tu most peripherals. 19257b55c76SYu Tu 19357b55c76SYu Tuconfig COMMON_CLK_S4_PERIPHERALS 19457b55c76SYu Tu tristate "S4 SoC peripherals clock controllers support" 19557b55c76SYu Tu depends on ARM64 1960afce85eSKrzysztof Kozlowski default ARCH_MESON 19798408df6SArnd Bergmann select COMMON_CLK_MESON_CLKC_UTILS 19857b55c76SYu Tu select COMMON_CLK_MESON_REGMAP 19957b55c76SYu Tu select COMMON_CLK_MESON_DUALDIV 20057b55c76SYu Tu select COMMON_CLK_MESON_VID_PLL_DIV 20157b55c76SYu Tu help 20257b55c76SYu Tu Support for the peripherals clock controller on Amlogic S805X2 and S905Y4 20357b55c76SYu Tu devices, AKA S4. Say Y if you want S4 peripherals clock controller to work. 2047b5c5720SJerome Brunetendmenu 205