Merge branch 'pci/controller/dwc-ultrarisc'

- Add UltraRISC DP1000 PCIe controller DT binding and driver (Jia Wang)

* pci/controller/dwc-ultrarisc:
PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root

Merge branch 'pci/controller/dwc-ultrarisc'

- Add UltraRISC DP1000 PCIe controller DT binding and driver (Jia Wang)

* pci/controller/dwc-ultrarisc:
PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver
dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

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PCI: imx6: Integrate new pwrctrl API

Integrate the PCI pwrctrl framework into the pci-imx6 driver to provide
standardized power management for PCI devices.

Legacy regulator handling (vpcie-supply a

PCI: imx6: Integrate new pwrctrl API

Integrate the PCI pwrctrl framework into the pci-imx6 driver to provide
standardized power management for PCI devices.

Legacy regulator handling (vpcie-supply at controller level) is maintained
for backward compatibility with existing device trees. New device trees
should specify power supplies at the Root Port level to utilize the pwrctrl
framework.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260520084904.2424253-2-sherry.sun@oss.nxp.com

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PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver

Add DP1000 SoC PCIe Root Complex driver.

The controller only supports 32-bit aligned configuration space accesses.

Signed-off-by: Xinc

PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver

Add DP1000 SoC PCIe Root Complex driver.

The controller only supports 32-bit aligned configuration space accesses.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
[mani: changed to builtin_platform_driver() to prevent irqchip removal]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: squash MAINTAINERS update here]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com

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Merge branch 'pci/controller/dwc-layerscape'

- Allow Layerscape host controller driver to be build as a removable module
(Sascha Hauer)

* pci/controller/dwc-layerscape:
PCI: layerscape: Allow t

Merge branch 'pci/controller/dwc-layerscape'

- Allow Layerscape host controller driver to be build as a removable module
(Sascha Hauer)

* pci/controller/dwc-layerscape:
PCI: layerscape: Allow to compile as module

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Merge branch 'pci/controller/dwc-eswin'

- Add DT binding and driver for ESWIN PCIe Root Complex (Senchuan Zhang)

* pci/controller/dwc-eswin:
PCI: eswin: Add ESWIN PCIe Root Complex driver
dt-bi

Merge branch 'pci/controller/dwc-eswin'

- Add DT binding and driver for ESWIN PCIe Root Complex (Senchuan Zhang)

* pci/controller/dwc-eswin:
PCI: eswin: Add ESWIN PCIe Root Complex driver
dt-bindings: PCI: eswin: Add ESWIN PCIe Root Complex

# Conflicts:
# drivers/pci/controller/dwc/Kconfig
# drivers/pci/controller/dwc/Makefile

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Merge branch 'pci/controller/dwc-andes-qilai'

- Add Andes QiLai SoC PCIe host driver support (Randolph Lin)

* pci/controller/dwc-andes-qilai:
PCI: qilai: Add Andes QiLai SoC PCIe host driver supp

Merge branch 'pci/controller/dwc-andes-qilai'

- Add Andes QiLai SoC PCIe host driver support (Randolph Lin)

* pci/controller/dwc-andes-qilai:
PCI: qilai: Add Andes QiLai SoC PCIe host driver support
dt-bindings: PCI: Add Andes QiLai PCIe support

# Conflicts:
# drivers/pci/controller/dwc/Makefile

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Merge branch 'pci/controller/dwc'

- Continue with system suspend even if an Endpoint doesn't respond with
PME_TO_Ack message (Manivannan Sadhasivam)

- Remove the Baikal-T1 controller driver since

Merge branch 'pci/controller/dwc'

- Continue with system suspend even if an Endpoint doesn't respond with
PME_TO_Ack message (Manivannan Sadhasivam)

- Remove the Baikal-T1 controller driver since it never quite became usable
(Andy Shevchenko)

- Set Endpoint MSI-X Table Size in the correct function of a multi-function
device when configuring MSI-X, not in Function 0 (Aksh Garg)

- Set Max Link Width and Max Link Speed for all functions of a
multi-function device, not just Function 0 (Aksh Garg)

- Clean up in the dw_pcie_resume_noirq() error path (Manivannan Sadhasivam)

- Expose PCIe event counters in groups 5-7 in debugfs (Hans Zhang)

- Fix type mismatch for kstrtou32_from_user() in debugfs write functions
(Hans Zhang)

* pci/controller/dwc:
PCI: dwc: Fix type mismatch for kstrtou32_from_user() return value
PCI: dwc: Expose PCIe event counters for groups 5 to 7 over debugfs
PCI: dwc: Perform cleanup in the error path of dw_pcie_resume_noirq()
PCI: dwc: ep: Mirror the max link width and speed fields to all functions
PCI: dwc: ep: Fix MSI-X Table Size configuration in dw_pcie_ep_set_msix()
PCI: dwc: Remove not-going-to-be-supported code for Baikal SoC
PCI: dwc: Proceed with system suspend even if the endpoint doesn't respond with PME_TO_Ack message

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PCI: eswin: Add ESWIN PCIe Root Complex driver

Add driver for the ESWIN PCIe Root Complex based on the DesignWare PCIe
core, IP revision 5.96a. The PCIe Gen.3 Root Complex supports data rate of
8 GT

PCI: eswin: Add ESWIN PCIe Root Complex driver

Add driver for the ESWIN PCIe Root Complex based on the DesignWare PCIe
core, IP revision 5.96a. The PCIe Gen.3 Root Complex supports data rate of
8 GT/s and x4 lanes, with INTx and MSI interrupt capability.

Signed-off-by: Yu Ning <ningyu@eswincomputing.com>
Signed-off-by: Yanghui Ou <ouyanghui@eswincomputing.com>
Signed-off-by: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
[mani: renamed "EIC7700" to "ESWIN", added maintainers entry, removed async probe]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: add driver tag in subject]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260227111808.1996-1-zhangsenchuan@eswincomputing.com

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PCI/pwrctrl: generic: Rename pci-pwrctrl-slot as generic

The driver is pretty generic and would fit for either PCI Slots or
endpoints connected to PCI ports, so rename the driver and module as
pci-p

PCI/pwrctrl: generic: Rename pci-pwrctrl-slot as generic

The driver is pretty generic and would fit for either PCI Slots or
endpoints connected to PCI ports, so rename the driver and module as
pci-pwrctrl-generic.

Suggested-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260220-topic-sm8650-ayaneo-pocket-s2-base-v5-3-1ad79caa1efa@linaro.org

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PCI: qilai: Add Andes QiLai SoC PCIe host driver support

Add driver support for DesignWare based PCIe controller in Andes
QiLai SoC. The driver only supports the Root Complex mode.

Signed-off-by: R

PCI: qilai: Add Andes QiLai SoC PCIe host driver support

Add driver support for DesignWare based PCIe controller in Andes
QiLai SoC. The driver only supports the Root Complex mode.

Signed-off-by: Randolph Lin <randolph@andestech.com>
[mani: squashed the MAINTAINERS change]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20260225085504.3757601-4-randolph@andestech.com

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PCI: dwc: Remove not-going-to-be-supported code for Baikal SoC

As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Signed-off-by: A

PCI: dwc: Remove not-going-to-be-supported code for Baikal SoC

As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]
Link: https://patch.msgid.link/20260220142600.2397070-1-andriy.shevchenko@linux.intel.com

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PCI: layerscape: Allow to compile as module

The layerscape pcie host controller could also be compiled as module.
Add the necessary infrastructure to allow building as module instead of
only as buil

PCI: layerscape: Allow to compile as module

The layerscape pcie host controller could also be compiled as module.
Add the necessary infrastructure to allow building as module instead of
only as builtin driver.

Since the driver doesn't expose an irqchip controller, it is also safe to
be removed during runtime.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
[mani: added a note about driver removability]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Roy Zang <Roy.Zang@nxp.com>
Link: https://patch.msgid.link/20260112-v6-19-topic-layerscape-pcie-v1-1-1cd863fce50e@pengutronix.de

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PCI: dwc: tegra194: Broaden architecture dependency

Replace ARCH_TEGRA_194_SOC dependency with a more generic ARCH_TEGRA check
for the Tegra194 PCIe controller, allowing it to be built on Tegra
plat

PCI: dwc: tegra194: Broaden architecture dependency

Replace ARCH_TEGRA_194_SOC dependency with a more generic ARCH_TEGRA check
for the Tegra194 PCIe controller, allowing it to be built on Tegra
platforms beyond Tegra194. Additionally, ensure compatibility by requiring
ARM64 or COMPILE_TEST since this driver works only for ARM64 Tegra SoCs.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
[mani: moved ARM64 dependency to ARCH_TEGRA]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Acked-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20250508051922.4134041-1-vidyas@nvidia.com

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Merge branch 'pci/controller/spacemit-k1'

- Add DT binding and driver for SpacemiT K1 (Alex Elder)

* pci/controller/spacemit-k1:
PCI: spacemit: Add SpacemiT PCIe host driver
dt-bindings: pci: s

Merge branch 'pci/controller/spacemit-k1'

- Add DT binding and driver for SpacemiT K1 (Alex Elder)

* pci/controller/spacemit-k1:
PCI: spacemit: Add SpacemiT PCIe host driver
dt-bindings: pci: spacemit: Introduce PCIe host controller

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Merge branch 'pci/controller/s32g'

- Add NXP S32G host controller DT binding and driver (Vincent Guittot)

* pci/controller/s32g:
MAINTAINERS: Add NXP S32G PCIe controller driver maintainer
PCI:

Merge branch 'pci/controller/s32g'

- Add NXP S32G host controller DT binding and driver (Vincent Guittot)

* pci/controller/s32g:
MAINTAINERS: Add NXP S32G PCIe controller driver maintainer
PCI: s32g: Add NXP S32G PCIe controller driver (RC)
PCI: dwc: Add register and bitfield definitions
dt-bindings: PCI: s32g: Add NXP S32G PCIe controller

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PCI: s32g: Add NXP S32G PCIe controller driver (RC)

Add initial support of the PCIe controller for the NXP S32G SoC family.
Only host mode is supported.

Co-developed-by: Ionut Vicovan <Ionut.Vicova

PCI: s32g: Add NXP S32G PCIe controller driver (RC)

Add initial support of the PCIe controller for the NXP S32G SoC family.
Only host mode is supported.

Co-developed-by: Ionut Vicovan <Ionut.Vicovan@nxp.com>
Signed-off-by: Ionut Vicovan <Ionut.Vicovan@nxp.com>
Co-developed-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com>
Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>
Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
[mani: replaced memblock_start_of_DRAM with hardcoded boundary addr]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251121164920.2008569-4-vincent.guittot@linaro.org

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PCI: spacemit: Add SpacemiT PCIe host driver

Introduce a driver for the PCIe host controller found in the SpacemiT K1
SoC. The hardware is derived from the Synopsys DesignWare PCIe IP. The
driver su

PCI: spacemit: Add SpacemiT PCIe host driver

Introduce a driver for the PCIe host controller found in the SpacemiT K1
SoC. The hardware is derived from the Synopsys DesignWare PCIe IP. The
driver supports up to three PCIe ports operating at PCIe link speed up to
5 GT/s. The first port uses a combo PHY, which may be configured for use
for USB3 instead.

Signed-off-by: Alex Elder <elder@riscstar.com>
[mani: added FIXME to the comment on disabling ASPM L1]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Jason Montleon <jmontleo@redhat.com>
Tested-by: Johannes Erdfelt <johannes@erdfelt.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Link: https://patch.msgid.link/20251113214540.2623070-6-elder@riscstar.com

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PCI: keystone: Add support to build as a loadable module

The 'pci-keystone.c' driver is the application/glue/wrapper driver for the
Designware PCIe Controllers on TI SoCs. Now that all of the helper

PCI: keystone: Add support to build as a loadable module

The 'pci-keystone.c' driver is the application/glue/wrapper driver for the
Designware PCIe Controllers on TI SoCs. Now that all of the helper APIs
that the 'pci-keystone.c' driver depends upon have been exported for use,
enable support to build the driver as a loadable module.

When building the driver as a module, the functions marked by the '__init'
keyword may be invoked after the init memory has been freed by the kernel.
This results will result in an exception of the form:

Unable to handle kernel paging request at virtual address ...
Mem abort info:
...
pc : ks_pcie_host_init+0x0/0x540
lr : dw_pcie_host_init+0x170/0x498
...
ks_pcie_host_init+0x0/0x540 (P)
ks_pcie_probe+0x728/0x84c
platform_probe+0x5c/0x98
really_probe+0xbc/0x29c
__driver_probe_device+0x78/0x12c
driver_probe_device+0xd8/0x15c

To address this, introduce a new function namely 'ks_pcie_init()' to
register the 'fault handler' while removing the '__init' keyword from
existing functions.

Note that hook_fault_code() is defined as '__init' function. Since the init
functions should never be called during runtime (after init memory freeing
stage), the driver is made as a built-in if CONFIG_ARM (where
hook_fault_code() is used) is selected.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[mani: added a note about hook_fault_code()]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20251029080547.1253757-5-s-vadapalli@ti.com

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Merge branch 'pci/controller/stm32'

- Update pinctrl documentation of initial states and use in runtime
suspend/resume (Christian Bruel)

- Add pinctrl_pm_select_init_state() for use by stm32 driv

Merge branch 'pci/controller/stm32'

- Update pinctrl documentation of initial states and use in runtime
suspend/resume (Christian Bruel)

- Add pinctrl_pm_select_init_state() for use by stm32 driver, which needs
it during resume (Christian Bruel)

- Add devicetree bindings and drivers for the STMicroelectronics STM32MP25
in host and endpoint modes (Christian Bruel)

* pci/controller/stm32:
MAINTAINERS: Add entry for ST STM32MP25 PCIe drivers
PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25
dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings
PCI: stm32: Add PCIe host support for STM32MP25
dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings
pinctrl: Add pinctrl_pm_select_init_state helper function
Documentation: pinctrl: Describe PM helper functions for standard states.

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PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25

Add driver to configure the STM32MP25 SoC PCIe controller based on the
DesignWare PCIe core in endpoint mode. Controller support 2.5 and 5 GT/s

PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25

Add driver to configure the STM32MP25 SoC PCIe controller based on the
DesignWare PCIe core in endpoint mode. Controller support 2.5 and 5 GT/s
data rates and uses the common reference clock provided by the host.

The PCIe core_clk receives the pipe0_clk from the ComboPHY as input,
and the ComboPHY PLL must be locked for pipe0_clk to be ready.
Consequently, PCIe core registers cannot be accessed until the ComboPHY is
fully initialised and REFCLK is enabled and ready.

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
[mani: reworded description]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: squash in https://patch.msgid.link/20250902122641.269725-1-christian.bruel@foss.st.com
to remove redundant link_status checks]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250820075411.1178729-7-christian.bruel@foss.st.com

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PCI: stm32: Add PCIe host support for STM32MP25

Add driver for the STM32MP25 SoC PCIe controller based on the DesignWare
PCIe core. Controller supports 2.5 and 5 GT/s data rates, MSI via GICv2m,
Sin

PCI: stm32: Add PCIe host support for STM32MP25

Add driver for the STM32MP25 SoC PCIe controller based on the DesignWare
PCIe core. Controller supports 2.5 and 5 GT/s data rates, MSI via GICv2m,
Single Virtual Channel, Single Function and WAKE# GPIO.

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
[mani: reworded description]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: squash error handling cleanup from Christophe JAILLET
<christophe.jaillet@wanadoo.fr>:
https://patch.msgid.link/e69ade3edcec4da2d5bfc66e0d03bbcb5a857021.1759169956.git.christophe.jaillet@wanadoo.fr]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250820075411.1178729-5-christian.bruel@foss.st.com

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PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'

In order to enable PCIe ECAM mechanism in DWC driver as per the 'CFG Shift
Feature' documented in Designware d

PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'

In order to enable PCIe ECAM mechanism in DWC driver as per the 'CFG Shift
Feature' documented in Designware databook r5.20a, sec 3.10.10.3, prepare
the driver to handle the one time iATU setup and creating ECAM window.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: splitted the preparatory code into a separate commit for bisectability]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250923-controller-dwc-ecam-v10-2-e84390ba75fa@kernel.org

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PCI: qcom: Select PCI Power Control Slot driver

Select the pwrctrl driver, which is utilized to manage the power supplies
of the devices connected to the standard PCI slots conforming to
specificati

PCI: qcom: Select PCI Power Control Slot driver

Select the pwrctrl driver, which is utilized to manage the power supplies
of the devices connected to the standard PCI slots conforming to
specification like PCIe CEM. This ensures that the voltage rails of the
standard PCI slots on some platforms eg. X1E80100-QCP can be correctly
turned on/off if they are described in PCIe Root Port device tree node.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
[mani: reworded subject and description]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250722091151.1423332-2-quic_wenbyao@quicinc.com

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Merge branch 'pci/controller/sophgo'

- Add DT binding and driver for Sophgo SG2044 PCIe controller driver in
Root Complex mode (Inochi Amaoto)

* pci/controller/sophgo:
PCI: dwc: Add Sophgo SG20

Merge branch 'pci/controller/sophgo'

- Add DT binding and driver for Sophgo SG2044 PCIe controller driver in
Root Complex mode (Inochi Amaoto)

* pci/controller/sophgo:
PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode
dt-bindings: pci: Add Sophgo SG2044 PCIe host

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Merge branch 'pci/controller/qcom'

- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM
implementation (Mayank Rana)

- Rename gen_pci_init() to pci_host_common_ecam_create(

Merge branch 'pci/controller/qcom'

- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM
implementation (Mayank Rana)

- Rename gen_pci_init() to pci_host_common_ecam_create() and export for use
by controller drivers (Mayank Rana)

- Add DT binding and driver support for SA8255p, which supports ECAM for
Configuration Space access (Mayank Rana)

- Update DT binding and driver to describe PHYs and per-Root Port resets in
a Root Port stanza and deprecate describing them in the host bridge; this
makes it possible to support multiple Root Ports in the future (Krishna
Chaitanya Chundru)

* pci/controller/qcom:
PCI: qcom: Add support for parsing the new Root Port binding
dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex
dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers
PCI: dwc: Export DWC MSI controller related APIs

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