1e0dda311SFrank Wunderlich# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2e0dda311SFrank Wunderlich%YAML 1.2 3e0dda311SFrank Wunderlich--- 4e0dda311SFrank Wunderlich$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5e0dda311SFrank Wunderlich$schema: http://devicetree.org/meta-schemas/core.yaml# 6e0dda311SFrank Wunderlich 7214537cdSArınç ÜNALtitle: Mediatek MT7530 and MT7531 Ethernet Switches 8e0dda311SFrank Wunderlich 9e0dda311SFrank Wunderlichmaintainers: 10214537cdSArınç ÜNAL - Arınç ÜNAL <arinc.unal@arinc9.com> 11e0dda311SFrank Wunderlich - Landen Chao <Landen.Chao@mediatek.com> 12e0dda311SFrank Wunderlich - DENG Qingfang <dqfext@gmail.com> 13214537cdSArınç ÜNAL - Sean Wang <sean.wang@mediatek.com> 14386f5fc9SDaniel Golle - Daniel Golle <daniel@makrotopia.org> 15e0dda311SFrank Wunderlich 16e0dda311SFrank Wunderlichdescription: | 17386f5fc9SDaniel Golle There are three versions of MT7530, standalone, in a multi-chip module and 18386f5fc9SDaniel Golle built-into a SoC. 19e0dda311SFrank Wunderlich 20cd7e2b97SArınç ÜNAL MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 21cd7e2b97SArınç ÜNAL MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 22e0dda311SFrank Wunderlich 23386f5fc9SDaniel Golle The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four 24386f5fc9SDaniel Golle Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's 25c0c68e4dSChris Packham memory map rather than using MDIO. The switch has an internally connected 10G 26386f5fc9SDaniel Golle CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs. 27386f5fc9SDaniel Golle 28c0c68e4dSChris Packham The MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has 10/100 PHYs 29cd7e2b97SArınç ÜNAL and the switch registers are directly mapped into SoC's memory map rather than 30386f5fc9SDaniel Golle using MDIO. The DSA driver currently doesn't support MT7620 variants. 31e0dda311SFrank Wunderlich 32cd7e2b97SArınç ÜNAL There is only the standalone version of MT7531. 33e0dda311SFrank Wunderlich 34c0c68e4dSChris Packham Port 5 on MT7530 supports various configurations: 35cd7e2b97SArınç ÜNAL 36cd7e2b97SArınç ÜNAL - Port 5 can be used as a CPU port. 37cd7e2b97SArınç ÜNAL 38a71fad0fSArınç ÜNAL - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, 39a71fad0fSArınç ÜNAL the gmac of the SoC which is wired to port 5 can connect to the PHY. 40a71fad0fSArınç ÜNAL This is usually used for connecting the wan port directly to the CPU to 41a71fad0fSArınç ÜNAL achieve 2 Gbps routing in total. 42cd7e2b97SArınç ÜNAL 43a71fad0fSArınç ÜNAL The driver looks up the reg on the ethernet-phy node, which the phy-handle 44a71fad0fSArınç ÜNAL property on the gmac node refers to, to mux the specified phy. 45cd7e2b97SArınç ÜNAL 46cd7e2b97SArınç ÜNAL The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 47a71fad0fSArınç ÜNAL compatible string and the reg must be 1. So, for now, only gmac1 of a 48cd7e2b97SArınç ÜNAL MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 49cd7e2b97SArınç ÜNAL 50cd7e2b97SArınç ÜNAL For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 51a71fad0fSArınç ÜNAL 52cd7e2b97SArınç ÜNAL Check out example 5. 53cd7e2b97SArınç ÜNAL 54a71fad0fSArınç ÜNAL - For the multi-chip module MT7530, in case of an external phy wired to 55a71fad0fSArınç ÜNAL gmac1 of the SoC, port 5 must not be enabled. 56cd7e2b97SArınç ÜNAL 57cd7e2b97SArınç ÜNAL In case of muxing PHY 0 or 4, the external phy must not be enabled. 58cd7e2b97SArınç ÜNAL 59cd7e2b97SArınç ÜNAL For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60a71fad0fSArınç ÜNAL 61cd7e2b97SArınç ÜNAL Check out example 6. 62cd7e2b97SArınç ÜNAL 636ca80638SFlorian Fainelli - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port. 64cd7e2b97SArınç ÜNAL 65a71fad0fSArınç ÜNAL For the multi-chip module MT7530, the external phy must be wired TX to TX 66a71fad0fSArınç ÜNAL to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired 67a71fad0fSArınç ÜNAL this way. 68a71fad0fSArınç ÜNAL 69a71fad0fSArınç ÜNAL For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the 70a71fad0fSArınç ÜNAL external phy is connected TX to TX. 71cd7e2b97SArınç ÜNAL 72cd7e2b97SArınç ÜNAL For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 73a71fad0fSArınç ÜNAL 74cd7e2b97SArınç ÜNAL Check out example 7. 75e0dda311SFrank Wunderlich 76e0dda311SFrank Wunderlichproperties: 77e0dda311SFrank Wunderlich compatible: 78214537cdSArınç ÜNAL oneOf: 79214537cdSArınç ÜNAL - description: 80214537cdSArınç ÜNAL Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 81214537cdSArınç ÜNAL const: mediatek,mt7530 82214537cdSArınç ÜNAL 83214537cdSArınç ÜNAL - description: 84214537cdSArınç ÜNAL Standalone MT7531 85214537cdSArınç ÜNAL const: mediatek,mt7531 86214537cdSArınç ÜNAL 87214537cdSArınç ÜNAL - description: 88214537cdSArınç ÜNAL Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 89214537cdSArınç ÜNAL const: mediatek,mt7621 90e0dda311SFrank Wunderlich 91386f5fc9SDaniel Golle - description: 92386f5fc9SDaniel Golle Built-in switch of the MT7988 SoC 93386f5fc9SDaniel Golle const: mediatek,mt7988-switch 94386f5fc9SDaniel Golle 95*101a002aSLorenzo Bianconi - description: 96*101a002aSLorenzo Bianconi Built-in switch of the Airoha EN7581 SoC 97*101a002aSLorenzo Bianconi const: airoha,en7581-switch 98*101a002aSLorenzo Bianconi 993359619aSRob Herring reg: 1003359619aSRob Herring maxItems: 1 1013359619aSRob Herring 102e0dda311SFrank Wunderlich core-supply: 103e0dda311SFrank Wunderlich description: 104e0dda311SFrank Wunderlich Phandle to the regulator node necessary for the core power. 105e0dda311SFrank Wunderlich 106e0dda311SFrank Wunderlich "#gpio-cells": 107e0dda311SFrank Wunderlich const: 2 108e0dda311SFrank Wunderlich 109e0dda311SFrank Wunderlich gpio-controller: 110e0dda311SFrank Wunderlich type: boolean 1117d8c4891SArınç ÜNAL description: | 1120fbca84eSArınç ÜNAL If defined, LED controller of the MT7530 switch will run on GPIO mode. 1130fbca84eSArınç ÜNAL 1140fbca84eSArınç ÜNAL There are 15 controllable pins. 1150fbca84eSArınç ÜNAL port 0 LED 0..2 as GPIO 0..2 1160fbca84eSArınç ÜNAL port 1 LED 0..2 as GPIO 3..5 1170fbca84eSArınç ÜNAL port 2 LED 0..2 as GPIO 6..8 1180fbca84eSArınç ÜNAL port 3 LED 0..2 as GPIO 9..11 1190fbca84eSArınç ÜNAL port 4 LED 0..2 as GPIO 12..14 120e0dda311SFrank Wunderlich 121e0dda311SFrank Wunderlich "#interrupt-cells": 122e0dda311SFrank Wunderlich const: 1 123e0dda311SFrank Wunderlich 124e0dda311SFrank Wunderlich interrupt-controller: true 125e0dda311SFrank Wunderlich 126e0dda311SFrank Wunderlich interrupts: 127e0dda311SFrank Wunderlich maxItems: 1 128e0dda311SFrank Wunderlich 129e0dda311SFrank Wunderlich io-supply: 1307d8c4891SArınç ÜNAL description: | 131e0dda311SFrank Wunderlich Phandle to the regulator node necessary for the I/O power. 132214537cdSArınç ÜNAL See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 133214537cdSArınç ÜNAL details for the regulator setup on these boards. 134e0dda311SFrank Wunderlich 135e0dda311SFrank Wunderlich mediatek,mcm: 136e0dda311SFrank Wunderlich type: boolean 137e0dda311SFrank Wunderlich description: 138ba9476f7SArınç ÜNAL Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 139ba9476f7SArınç ÜNAL switch is a part of the multi-chip module. 140e0dda311SFrank Wunderlich 141e0dda311SFrank Wunderlich reset-gpios: 1427d8c4891SArınç ÜNAL description: | 143f565c54eSArınç ÜNAL GPIO to reset the switch. Use this if mediatek,mcm is not used. 144f565c54eSArınç ÜNAL This property is optional because some boards share the reset line with 145f565c54eSArınç ÜNAL other components which makes it impossible to probe the switch if the 146f565c54eSArınç ÜNAL reset line is used. 147e0dda311SFrank Wunderlich maxItems: 1 148e0dda311SFrank Wunderlich 149e0dda311SFrank Wunderlich reset-names: 150e0dda311SFrank Wunderlich const: mcm 151e0dda311SFrank Wunderlich 152e0dda311SFrank Wunderlich resets: 153e0dda311SFrank Wunderlich description: 154214537cdSArınç ÜNAL Phandle pointing to the system reset controller with line index for the 155214537cdSArınç ÜNAL ethsys. 156e0dda311SFrank Wunderlich maxItems: 1 157e0dda311SFrank Wunderlich 158e0dda311SFrank WunderlichpatternProperties: 159e0dda311SFrank Wunderlich "^(ethernet-)?ports$": 160e0dda311SFrank Wunderlich type: object 161659fd097SRob Herring additionalProperties: true 162e0dda311SFrank Wunderlich 163e0dda311SFrank Wunderlich patternProperties: 16451ff5150SRob Herring "^(ethernet-)?port@[0-6]$": 165e0dda311SFrank Wunderlich type: object 166659fd097SRob Herring additionalProperties: true 167e0dda311SFrank Wunderlich 168e0dda311SFrank Wunderlich properties: 169e0dda311SFrank Wunderlich reg: 170e0dda311SFrank Wunderlich description: 171214537cdSArınç ÜNAL Port address described must be 5 or 6 for CPU port and from 0 to 5 172214537cdSArınç ÜNAL for user ports. 173e0dda311SFrank Wunderlich 174e0dda311SFrank Wunderlich allOf: 175e0dda311SFrank Wunderlich - if: 1763f301a28SVladimir Oltean required: [ ethernet ] 177e0dda311SFrank Wunderlich then: 178214537cdSArınç ÜNAL properties: 179214537cdSArınç ÜNAL reg: 180214537cdSArınç ÜNAL enum: 181214537cdSArınç ÜNAL - 5 182214537cdSArınç ÜNAL - 6 183214537cdSArınç ÜNAL 184e0dda311SFrank Wunderlichrequired: 185e0dda311SFrank Wunderlich - compatible 186e0dda311SFrank Wunderlich - reg 187e0dda311SFrank Wunderlich 18879a16c3bSArınç ÜNAL$defs: 18979a16c3bSArınç ÜNAL mt7530-dsa-port: 19079a16c3bSArınç ÜNAL patternProperties: 19179a16c3bSArınç ÜNAL "^(ethernet-)?ports$": 19279a16c3bSArınç ÜNAL patternProperties: 19351ff5150SRob Herring "^(ethernet-)?port@[0-6]$": 19479a16c3bSArınç ÜNAL if: 1953f301a28SVladimir Oltean required: [ ethernet ] 19679a16c3bSArınç ÜNAL then: 19779a16c3bSArınç ÜNAL if: 19879a16c3bSArınç ÜNAL properties: 19979a16c3bSArınç ÜNAL reg: 20079a16c3bSArınç ÜNAL const: 5 20179a16c3bSArınç ÜNAL then: 20279a16c3bSArınç ÜNAL properties: 20379a16c3bSArınç ÜNAL phy-mode: 20479a16c3bSArınç ÜNAL enum: 20579a16c3bSArınç ÜNAL - gmii 20679a16c3bSArınç ÜNAL - mii 20779a16c3bSArınç ÜNAL - rgmii 20879a16c3bSArınç ÜNAL else: 20979a16c3bSArınç ÜNAL properties: 21079a16c3bSArınç ÜNAL phy-mode: 21179a16c3bSArınç ÜNAL enum: 21279a16c3bSArınç ÜNAL - rgmii 21379a16c3bSArınç ÜNAL - trgmii 21479a16c3bSArınç ÜNAL 21579a16c3bSArınç ÜNAL mt7531-dsa-port: 21679a16c3bSArınç ÜNAL patternProperties: 21779a16c3bSArınç ÜNAL "^(ethernet-)?ports$": 21879a16c3bSArınç ÜNAL patternProperties: 21951ff5150SRob Herring "^(ethernet-)?port@[0-6]$": 22079a16c3bSArınç ÜNAL if: 2213f301a28SVladimir Oltean required: [ ethernet ] 22279a16c3bSArınç ÜNAL then: 22379a16c3bSArınç ÜNAL if: 22479a16c3bSArınç ÜNAL properties: 22579a16c3bSArınç ÜNAL reg: 22679a16c3bSArınç ÜNAL const: 5 22779a16c3bSArınç ÜNAL then: 22879a16c3bSArınç ÜNAL properties: 22979a16c3bSArınç ÜNAL phy-mode: 23079a16c3bSArınç ÜNAL enum: 23179a16c3bSArınç ÜNAL - 1000base-x 23279a16c3bSArınç ÜNAL - 2500base-x 23379a16c3bSArınç ÜNAL - rgmii 23479a16c3bSArınç ÜNAL - sgmii 23579a16c3bSArınç ÜNAL else: 23679a16c3bSArınç ÜNAL properties: 23779a16c3bSArınç ÜNAL phy-mode: 23879a16c3bSArınç ÜNAL enum: 23979a16c3bSArınç ÜNAL - 1000base-x 24079a16c3bSArınç ÜNAL - 2500base-x 24179a16c3bSArınç ÜNAL - sgmii 24279a16c3bSArınç ÜNAL 243e0dda311SFrank WunderlichallOf: 2443cec368aSColin Foster - $ref: dsa.yaml#/$defs/ethernet-ports 245e0dda311SFrank Wunderlich - if: 246e0dda311SFrank Wunderlich required: 247e0dda311SFrank Wunderlich - mediatek,mcm 248e0dda311SFrank Wunderlich then: 249f565c54eSArınç ÜNAL properties: 250f565c54eSArınç ÜNAL reset-gpios: false 251f565c54eSArınç ÜNAL 252e0dda311SFrank Wunderlich required: 253e0dda311SFrank Wunderlich - resets 254e0dda311SFrank Wunderlich - reset-names 255e0dda311SFrank Wunderlich 256e0dda311SFrank Wunderlich - dependencies: 257e0dda311SFrank Wunderlich interrupt-controller: [ interrupts ] 258e0dda311SFrank Wunderlich 259e0dda311SFrank Wunderlich - if: 260e0dda311SFrank Wunderlich properties: 261e0dda311SFrank Wunderlich compatible: 262214537cdSArınç ÜNAL const: mediatek,mt7530 263e0dda311SFrank Wunderlich then: 26479a16c3bSArınç ÜNAL $ref: "#/$defs/mt7530-dsa-port" 265e0dda311SFrank Wunderlich required: 266e0dda311SFrank Wunderlich - core-supply 267e0dda311SFrank Wunderlich - io-supply 268e0dda311SFrank Wunderlich 269f565c54eSArınç ÜNAL - if: 270f565c54eSArınç ÜNAL properties: 271f565c54eSArınç ÜNAL compatible: 272f565c54eSArınç ÜNAL const: mediatek,mt7531 273f565c54eSArınç ÜNAL then: 27479a16c3bSArınç ÜNAL $ref: "#/$defs/mt7531-dsa-port" 275f565c54eSArınç ÜNAL properties: 2760fbca84eSArınç ÜNAL gpio-controller: false 277f565c54eSArınç ÜNAL mediatek,mcm: false 278f565c54eSArınç ÜNAL 279f565c54eSArınç ÜNAL - if: 280f565c54eSArınç ÜNAL properties: 281f565c54eSArınç ÜNAL compatible: 282f565c54eSArınç ÜNAL const: mediatek,mt7621 283f565c54eSArınç ÜNAL then: 28479a16c3bSArınç ÜNAL $ref: "#/$defs/mt7530-dsa-port" 285f565c54eSArınç ÜNAL required: 286f565c54eSArınç ÜNAL - mediatek,mcm 287f565c54eSArınç ÜNAL 288386f5fc9SDaniel Golle - if: 289386f5fc9SDaniel Golle properties: 290386f5fc9SDaniel Golle compatible: 291*101a002aSLorenzo Bianconi enum: 292*101a002aSLorenzo Bianconi - mediatek,mt7988-switch 293*101a002aSLorenzo Bianconi - airoha,en7581-switch 294386f5fc9SDaniel Golle then: 295386f5fc9SDaniel Golle $ref: "#/$defs/mt7530-dsa-port" 296386f5fc9SDaniel Golle properties: 297386f5fc9SDaniel Golle gpio-controller: false 298386f5fc9SDaniel Golle mediatek,mcm: false 299386f5fc9SDaniel Golle reset-names: false 300386f5fc9SDaniel Golle 301e0dda311SFrank WunderlichunevaluatedProperties: false 302e0dda311SFrank Wunderlich 303e0dda311SFrank Wunderlichexamples: 304c9aece04SArınç ÜNAL # Example 1: Standalone MT7530 305e0dda311SFrank Wunderlich - | 306e0dda311SFrank Wunderlich #include <dt-bindings/gpio/gpio.h> 307c9aece04SArınç ÜNAL 308e0dda311SFrank Wunderlich mdio { 309e0dda311SFrank Wunderlich #address-cells = <1>; 310e0dda311SFrank Wunderlich #size-cells = <0>; 311c9aece04SArınç ÜNAL 3123737c6aaSArınç ÜNAL switch@1f { 313e0dda311SFrank Wunderlich compatible = "mediatek,mt7530"; 3143737c6aaSArınç ÜNAL reg = <0x1f>; 315e0dda311SFrank Wunderlich 316c9aece04SArınç ÜNAL reset-gpios = <&pio 33 0>; 317c9aece04SArınç ÜNAL 318e0dda311SFrank Wunderlich core-supply = <&mt6323_vpa_reg>; 319e0dda311SFrank Wunderlich io-supply = <&mt6323_vemc3v3_reg>; 320e0dda311SFrank Wunderlich 321e0dda311SFrank Wunderlich ethernet-ports { 322e0dda311SFrank Wunderlich #address-cells = <1>; 323e0dda311SFrank Wunderlich #size-cells = <0>; 324c9aece04SArınç ÜNAL 325e0dda311SFrank Wunderlich port@0 { 326e0dda311SFrank Wunderlich reg = <0>; 327c9aece04SArınç ÜNAL label = "lan1"; 328e0dda311SFrank Wunderlich }; 329e0dda311SFrank Wunderlich 330e0dda311SFrank Wunderlich port@1 { 331e0dda311SFrank Wunderlich reg = <1>; 332c9aece04SArınç ÜNAL label = "lan2"; 333e0dda311SFrank Wunderlich }; 334e0dda311SFrank Wunderlich 335e0dda311SFrank Wunderlich port@2 { 336e0dda311SFrank Wunderlich reg = <2>; 337c9aece04SArınç ÜNAL label = "lan3"; 338e0dda311SFrank Wunderlich }; 339e0dda311SFrank Wunderlich 340e0dda311SFrank Wunderlich port@3 { 341e0dda311SFrank Wunderlich reg = <3>; 342c9aece04SArınç ÜNAL label = "lan4"; 343c9aece04SArınç ÜNAL }; 344c9aece04SArınç ÜNAL 345c9aece04SArınç ÜNAL port@4 { 346c9aece04SArınç ÜNAL reg = <4>; 347c9aece04SArınç ÜNAL label = "wan"; 348c9aece04SArınç ÜNAL }; 349c9aece04SArınç ÜNAL 350c9aece04SArınç ÜNAL port@6 { 351c9aece04SArınç ÜNAL reg = <6>; 352c9aece04SArınç ÜNAL ethernet = <&gmac0>; 353c9aece04SArınç ÜNAL phy-mode = "rgmii"; 354c9aece04SArınç ÜNAL 355c9aece04SArınç ÜNAL fixed-link { 356c9aece04SArınç ÜNAL speed = <1000>; 357c9aece04SArınç ÜNAL full-duplex; 358c9aece04SArınç ÜNAL pause; 359c9aece04SArınç ÜNAL }; 360c9aece04SArınç ÜNAL }; 361c9aece04SArınç ÜNAL }; 362c9aece04SArınç ÜNAL }; 363c9aece04SArınç ÜNAL }; 364c9aece04SArınç ÜNAL 365c9aece04SArınç ÜNAL # Example 2: MT7530 in MT7623AI SoC 366c9aece04SArınç ÜNAL - | 367c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt2701-resets.h> 368c9aece04SArınç ÜNAL 369c9aece04SArınç ÜNAL mdio { 370c9aece04SArınç ÜNAL #address-cells = <1>; 371c9aece04SArınç ÜNAL #size-cells = <0>; 372c9aece04SArınç ÜNAL 3733737c6aaSArınç ÜNAL switch@1f { 374c9aece04SArınç ÜNAL compatible = "mediatek,mt7530"; 3753737c6aaSArınç ÜNAL reg = <0x1f>; 376c9aece04SArınç ÜNAL 377c9aece04SArınç ÜNAL mediatek,mcm; 378c9aece04SArınç ÜNAL resets = <ðsys MT2701_ETHSYS_MCM_RST>; 379c9aece04SArınç ÜNAL reset-names = "mcm"; 380c9aece04SArınç ÜNAL 381c9aece04SArınç ÜNAL core-supply = <&mt6323_vpa_reg>; 382c9aece04SArınç ÜNAL io-supply = <&mt6323_vemc3v3_reg>; 383c9aece04SArınç ÜNAL 384c9aece04SArınç ÜNAL ethernet-ports { 385c9aece04SArınç ÜNAL #address-cells = <1>; 386c9aece04SArınç ÜNAL #size-cells = <0>; 387c9aece04SArınç ÜNAL 388c9aece04SArınç ÜNAL port@0 { 389c9aece04SArınç ÜNAL reg = <0>; 390c9aece04SArınç ÜNAL label = "lan1"; 391c9aece04SArınç ÜNAL }; 392c9aece04SArınç ÜNAL 393c9aece04SArınç ÜNAL port@1 { 394c9aece04SArınç ÜNAL reg = <1>; 395c9aece04SArınç ÜNAL label = "lan2"; 396c9aece04SArınç ÜNAL }; 397c9aece04SArınç ÜNAL 398c9aece04SArınç ÜNAL port@2 { 399c9aece04SArınç ÜNAL reg = <2>; 400e0dda311SFrank Wunderlich label = "lan3"; 401e0dda311SFrank Wunderlich }; 402e0dda311SFrank Wunderlich 403c9aece04SArınç ÜNAL port@3 { 404c9aece04SArınç ÜNAL reg = <3>; 405c9aece04SArınç ÜNAL label = "lan4"; 406c9aece04SArınç ÜNAL }; 407c9aece04SArınç ÜNAL 408e0dda311SFrank Wunderlich port@4 { 409e0dda311SFrank Wunderlich reg = <4>; 410e0dda311SFrank Wunderlich label = "wan"; 411e0dda311SFrank Wunderlich }; 412e0dda311SFrank Wunderlich 413e0dda311SFrank Wunderlich port@6 { 414e0dda311SFrank Wunderlich reg = <6>; 415e0dda311SFrank Wunderlich ethernet = <&gmac0>; 416e0dda311SFrank Wunderlich phy-mode = "trgmii"; 417e0dda311SFrank Wunderlich 418e0dda311SFrank Wunderlich fixed-link { 419e0dda311SFrank Wunderlich speed = <1000>; 420e0dda311SFrank Wunderlich full-duplex; 421e0dda311SFrank Wunderlich pause; 422e0dda311SFrank Wunderlich }; 423e0dda311SFrank Wunderlich }; 424c9aece04SArınç ÜNAL }; 425c9aece04SArınç ÜNAL }; 426e0dda311SFrank Wunderlich }; 427e0dda311SFrank Wunderlich 428c9aece04SArınç ÜNAL # Example 3: Standalone MT7531 429c9aece04SArınç ÜNAL - | 430c9aece04SArınç ÜNAL #include <dt-bindings/gpio/gpio.h> 431c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/irq.h> 432c9aece04SArınç ÜNAL 433c9aece04SArınç ÜNAL mdio { 434e0dda311SFrank Wunderlich #address-cells = <1>; 435e0dda311SFrank Wunderlich #size-cells = <0>; 436e0dda311SFrank Wunderlich 437c9aece04SArınç ÜNAL switch@0 { 438c9aece04SArınç ÜNAL compatible = "mediatek,mt7531"; 439c9aece04SArınç ÜNAL reg = <0>; 440e0dda311SFrank Wunderlich 441c9aece04SArınç ÜNAL reset-gpios = <&pio 54 0>; 442e0dda311SFrank Wunderlich 443c9aece04SArınç ÜNAL interrupt-controller; 444c9aece04SArınç ÜNAL #interrupt-cells = <1>; 445c9aece04SArınç ÜNAL interrupt-parent = <&pio>; 446c9aece04SArınç ÜNAL interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 447e0dda311SFrank Wunderlich 448e0dda311SFrank Wunderlich ethernet-ports { 449e0dda311SFrank Wunderlich #address-cells = <1>; 450e0dda311SFrank Wunderlich #size-cells = <0>; 451e0dda311SFrank Wunderlich 452e0dda311SFrank Wunderlich port@0 { 453e0dda311SFrank Wunderlich reg = <0>; 454c9aece04SArınç ÜNAL label = "lan1"; 455e0dda311SFrank Wunderlich }; 456e0dda311SFrank Wunderlich 457e0dda311SFrank Wunderlich port@1 { 458e0dda311SFrank Wunderlich reg = <1>; 459c9aece04SArınç ÜNAL label = "lan2"; 460e0dda311SFrank Wunderlich }; 461e0dda311SFrank Wunderlich 462e0dda311SFrank Wunderlich port@2 { 463e0dda311SFrank Wunderlich reg = <2>; 464c9aece04SArınç ÜNAL label = "lan3"; 465e0dda311SFrank Wunderlich }; 466e0dda311SFrank Wunderlich 467e0dda311SFrank Wunderlich port@3 { 468e0dda311SFrank Wunderlich reg = <3>; 469c9aece04SArınç ÜNAL label = "lan4"; 470c9aece04SArınç ÜNAL }; 471c9aece04SArınç ÜNAL 472c9aece04SArınç ÜNAL port@4 { 473c9aece04SArınç ÜNAL reg = <4>; 474c9aece04SArınç ÜNAL label = "wan"; 475c9aece04SArınç ÜNAL }; 476c9aece04SArınç ÜNAL 477c9aece04SArınç ÜNAL port@6 { 478c9aece04SArınç ÜNAL reg = <6>; 479c9aece04SArınç ÜNAL ethernet = <&gmac0>; 480c9aece04SArınç ÜNAL phy-mode = "2500base-x"; 481c9aece04SArınç ÜNAL 482c9aece04SArınç ÜNAL fixed-link { 483c9aece04SArınç ÜNAL speed = <2500>; 484c9aece04SArınç ÜNAL full-duplex; 485c9aece04SArınç ÜNAL pause; 486c9aece04SArınç ÜNAL }; 487c9aece04SArınç ÜNAL }; 488c9aece04SArınç ÜNAL }; 489c9aece04SArınç ÜNAL }; 490c9aece04SArınç ÜNAL }; 491c9aece04SArınç ÜNAL 492c9aece04SArınç ÜNAL # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 493c9aece04SArınç ÜNAL - | 494c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 495c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 496c9aece04SArınç ÜNAL 497c9aece04SArınç ÜNAL mdio { 498c9aece04SArınç ÜNAL #address-cells = <1>; 499c9aece04SArınç ÜNAL #size-cells = <0>; 500c9aece04SArınç ÜNAL 5013737c6aaSArınç ÜNAL switch@1f { 502c9aece04SArınç ÜNAL compatible = "mediatek,mt7621"; 5033737c6aaSArınç ÜNAL reg = <0x1f>; 504c9aece04SArınç ÜNAL 505c9aece04SArınç ÜNAL mediatek,mcm; 506c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 507c9aece04SArınç ÜNAL reset-names = "mcm"; 508c9aece04SArınç ÜNAL 509c9aece04SArınç ÜNAL interrupt-controller; 510c9aece04SArınç ÜNAL #interrupt-cells = <1>; 511c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 512c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 513c9aece04SArınç ÜNAL 514c9aece04SArınç ÜNAL ethernet-ports { 515c9aece04SArınç ÜNAL #address-cells = <1>; 516c9aece04SArınç ÜNAL #size-cells = <0>; 517c9aece04SArınç ÜNAL 518c9aece04SArınç ÜNAL port@0 { 519c9aece04SArınç ÜNAL reg = <0>; 520c9aece04SArınç ÜNAL label = "lan1"; 521c9aece04SArınç ÜNAL }; 522c9aece04SArınç ÜNAL 523c9aece04SArınç ÜNAL port@1 { 524c9aece04SArınç ÜNAL reg = <1>; 525c9aece04SArınç ÜNAL label = "lan2"; 526c9aece04SArınç ÜNAL }; 527c9aece04SArınç ÜNAL 528c9aece04SArınç ÜNAL port@2 { 529c9aece04SArınç ÜNAL reg = <2>; 530e0dda311SFrank Wunderlich label = "lan3"; 531e0dda311SFrank Wunderlich }; 532e0dda311SFrank Wunderlich 533c9aece04SArınç ÜNAL port@3 { 534c9aece04SArınç ÜNAL reg = <3>; 535c9aece04SArınç ÜNAL label = "lan4"; 536c9aece04SArınç ÜNAL }; 537c9aece04SArınç ÜNAL 538e0dda311SFrank Wunderlich port@4 { 539e0dda311SFrank Wunderlich reg = <4>; 540c9aece04SArınç ÜNAL label = "wan"; 541c9aece04SArınç ÜNAL }; 542c9aece04SArınç ÜNAL 543c9aece04SArınç ÜNAL port@6 { 544c9aece04SArınç ÜNAL reg = <6>; 545c9aece04SArınç ÜNAL ethernet = <&gmac0>; 546c9aece04SArınç ÜNAL phy-mode = "trgmii"; 547c9aece04SArınç ÜNAL 548c9aece04SArınç ÜNAL fixed-link { 549c9aece04SArınç ÜNAL speed = <1000>; 550c9aece04SArınç ÜNAL full-duplex; 551c9aece04SArınç ÜNAL pause; 552c9aece04SArınç ÜNAL }; 553c9aece04SArınç ÜNAL }; 554c9aece04SArınç ÜNAL }; 555c9aece04SArınç ÜNAL }; 556c9aece04SArınç ÜNAL }; 557c9aece04SArınç ÜNAL 558c9aece04SArınç ÜNAL # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 559c9aece04SArınç ÜNAL - | 560c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 561c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 562c9aece04SArınç ÜNAL 563c9aece04SArınç ÜNAL ethernet { 564c9aece04SArınç ÜNAL #address-cells = <1>; 565c9aece04SArınç ÜNAL #size-cells = <0>; 566c9aece04SArınç ÜNAL 567c9aece04SArınç ÜNAL pinctrl-names = "default"; 568c9aece04SArınç ÜNAL pinctrl-0 = <&rgmii2_pins>; 569c9aece04SArınç ÜNAL 570c9aece04SArınç ÜNAL mac@1 { 571c9aece04SArınç ÜNAL compatible = "mediatek,eth-mac"; 572c9aece04SArınç ÜNAL reg = <1>; 573c9aece04SArınç ÜNAL 574c9aece04SArınç ÜNAL phy-mode = "rgmii"; 575c9aece04SArınç ÜNAL phy-handle = <&example5_ethphy4>; 576c9aece04SArınç ÜNAL }; 577c9aece04SArınç ÜNAL 578c9aece04SArınç ÜNAL mdio { 579c9aece04SArınç ÜNAL #address-cells = <1>; 580c9aece04SArınç ÜNAL #size-cells = <0>; 581c9aece04SArınç ÜNAL 582c9aece04SArınç ÜNAL /* MT7530's phy4 */ 583c9aece04SArınç ÜNAL example5_ethphy4: ethernet-phy@4 { 584c9aece04SArınç ÜNAL reg = <4>; 585c9aece04SArınç ÜNAL }; 586c9aece04SArınç ÜNAL 5873737c6aaSArınç ÜNAL switch@1f { 588c9aece04SArınç ÜNAL compatible = "mediatek,mt7621"; 5893737c6aaSArınç ÜNAL reg = <0x1f>; 590c9aece04SArınç ÜNAL 591c9aece04SArınç ÜNAL mediatek,mcm; 592c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 593c9aece04SArınç ÜNAL reset-names = "mcm"; 594c9aece04SArınç ÜNAL 595c9aece04SArınç ÜNAL interrupt-controller; 596c9aece04SArınç ÜNAL #interrupt-cells = <1>; 597c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 598c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 599c9aece04SArınç ÜNAL 600c9aece04SArınç ÜNAL ethernet-ports { 601c9aece04SArınç ÜNAL #address-cells = <1>; 602c9aece04SArınç ÜNAL #size-cells = <0>; 603c9aece04SArınç ÜNAL 604c9aece04SArınç ÜNAL port@0 { 605c9aece04SArınç ÜNAL reg = <0>; 606c9aece04SArınç ÜNAL label = "lan1"; 607c9aece04SArınç ÜNAL }; 608c9aece04SArınç ÜNAL 609c9aece04SArınç ÜNAL port@1 { 610c9aece04SArınç ÜNAL reg = <1>; 611c9aece04SArınç ÜNAL label = "lan2"; 612c9aece04SArınç ÜNAL }; 613c9aece04SArınç ÜNAL 614c9aece04SArınç ÜNAL port@2 { 615c9aece04SArınç ÜNAL reg = <2>; 616c9aece04SArınç ÜNAL label = "lan3"; 617c9aece04SArınç ÜNAL }; 618c9aece04SArınç ÜNAL 619c9aece04SArınç ÜNAL port@3 { 620c9aece04SArınç ÜNAL reg = <3>; 621e0dda311SFrank Wunderlich label = "lan4"; 622e0dda311SFrank Wunderlich }; 623c9aece04SArınç ÜNAL 624a71fad0fSArınç ÜNAL /* Commented out, phy4 is connected to gmac1. 625c9aece04SArınç ÜNAL port@4 { 626c9aece04SArınç ÜNAL reg = <4>; 627c9aece04SArınç ÜNAL label = "wan"; 628c9aece04SArınç ÜNAL }; 629e0dda311SFrank Wunderlich */ 630e0dda311SFrank Wunderlich 631e0dda311SFrank Wunderlich port@6 { 632e0dda311SFrank Wunderlich reg = <6>; 633e0dda311SFrank Wunderlich ethernet = <&gmac0>; 634c9aece04SArınç ÜNAL phy-mode = "trgmii"; 635e0dda311SFrank Wunderlich 636e0dda311SFrank Wunderlich fixed-link { 637e0dda311SFrank Wunderlich speed = <1000>; 638e0dda311SFrank Wunderlich full-duplex; 639e0dda311SFrank Wunderlich pause; 640e0dda311SFrank Wunderlich }; 641e0dda311SFrank Wunderlich }; 642e0dda311SFrank Wunderlich }; 643e0dda311SFrank Wunderlich }; 644e0dda311SFrank Wunderlich }; 645e0dda311SFrank Wunderlich }; 646e0dda311SFrank Wunderlich 647c9aece04SArınç ÜNAL # Example 6: MT7621: mux external phy to SoC's gmac1 648e0dda311SFrank Wunderlich - | 649c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 650c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 651e0dda311SFrank Wunderlich 652e0dda311SFrank Wunderlich ethernet { 653e0dda311SFrank Wunderlich #address-cells = <1>; 654e0dda311SFrank Wunderlich #size-cells = <0>; 655c9aece04SArınç ÜNAL 656c9aece04SArınç ÜNAL pinctrl-names = "default"; 657c9aece04SArınç ÜNAL pinctrl-0 = <&rgmii2_pins>; 658c9aece04SArınç ÜNAL 659c9aece04SArınç ÜNAL mac@1 { 660e0dda311SFrank Wunderlich compatible = "mediatek,eth-mac"; 661c9aece04SArınç ÜNAL reg = <1>; 662c9aece04SArınç ÜNAL 663e0dda311SFrank Wunderlich phy-mode = "rgmii"; 664c9aece04SArınç ÜNAL phy-handle = <&example6_ethphy7>; 665e0dda311SFrank Wunderlich }; 666e0dda311SFrank Wunderlich 667c9aece04SArınç ÜNAL mdio { 668e0dda311SFrank Wunderlich #address-cells = <1>; 669e0dda311SFrank Wunderlich #size-cells = <0>; 670e0dda311SFrank Wunderlich 671c9aece04SArınç ÜNAL /* External PHY */ 672c9aece04SArınç ÜNAL example6_ethphy7: ethernet-phy@7 { 673e0dda311SFrank Wunderlich reg = <7>; 674c9aece04SArınç ÜNAL phy-mode = "rgmii"; 675e0dda311SFrank Wunderlich }; 676e0dda311SFrank Wunderlich 6773737c6aaSArınç ÜNAL switch@1f { 678e0dda311SFrank Wunderlich compatible = "mediatek,mt7621"; 6793737c6aaSArınç ÜNAL reg = <0x1f>; 680e0dda311SFrank Wunderlich 681c9aece04SArınç ÜNAL mediatek,mcm; 682c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 683e0dda311SFrank Wunderlich reset-names = "mcm"; 684e0dda311SFrank Wunderlich 685c9aece04SArınç ÜNAL interrupt-controller; 686c9aece04SArınç ÜNAL #interrupt-cells = <1>; 687c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 688c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 689c9aece04SArınç ÜNAL 690e0dda311SFrank Wunderlich ethernet-ports { 691e0dda311SFrank Wunderlich #address-cells = <1>; 692e0dda311SFrank Wunderlich #size-cells = <0>; 693e0dda311SFrank Wunderlich 694e0dda311SFrank Wunderlich port@0 { 695e0dda311SFrank Wunderlich reg = <0>; 696c9aece04SArınç ÜNAL label = "lan1"; 697e0dda311SFrank Wunderlich }; 698e0dda311SFrank Wunderlich 699e0dda311SFrank Wunderlich port@1 { 700e0dda311SFrank Wunderlich reg = <1>; 701c9aece04SArınç ÜNAL label = "lan2"; 702e0dda311SFrank Wunderlich }; 703e0dda311SFrank Wunderlich 704e0dda311SFrank Wunderlich port@2 { 705e0dda311SFrank Wunderlich reg = <2>; 706c9aece04SArınç ÜNAL label = "lan3"; 707e0dda311SFrank Wunderlich }; 708e0dda311SFrank Wunderlich 709e0dda311SFrank Wunderlich port@3 { 710e0dda311SFrank Wunderlich reg = <3>; 711c9aece04SArınç ÜNAL label = "lan4"; 712e0dda311SFrank Wunderlich }; 713e0dda311SFrank Wunderlich 714e0dda311SFrank Wunderlich port@4 { 715e0dda311SFrank Wunderlich reg = <4>; 716c9aece04SArınç ÜNAL label = "wan"; 717c9aece04SArınç ÜNAL }; 718c9aece04SArınç ÜNAL 719c9aece04SArınç ÜNAL port@6 { 720c9aece04SArınç ÜNAL reg = <6>; 721c9aece04SArınç ÜNAL ethernet = <&gmac0>; 722c9aece04SArınç ÜNAL phy-mode = "trgmii"; 723c9aece04SArınç ÜNAL 724c9aece04SArınç ÜNAL fixed-link { 725c9aece04SArınç ÜNAL speed = <1000>; 726c9aece04SArınç ÜNAL full-duplex; 727c9aece04SArınç ÜNAL pause; 728c9aece04SArınç ÜNAL }; 729c9aece04SArınç ÜNAL }; 730c9aece04SArınç ÜNAL }; 731c9aece04SArınç ÜNAL }; 732c9aece04SArınç ÜNAL }; 733c9aece04SArınç ÜNAL }; 734c9aece04SArınç ÜNAL 735c9aece04SArınç ÜNAL # Example 7: MT7621: mux external phy to MT7530's port 5 736c9aece04SArınç ÜNAL - | 737c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 738c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 739c9aece04SArınç ÜNAL 740c9aece04SArınç ÜNAL ethernet { 741c9aece04SArınç ÜNAL #address-cells = <1>; 742c9aece04SArınç ÜNAL #size-cells = <0>; 743c9aece04SArınç ÜNAL 744c9aece04SArınç ÜNAL pinctrl-names = "default"; 745c9aece04SArınç ÜNAL pinctrl-0 = <&rgmii2_pins>; 746c9aece04SArınç ÜNAL 747c9aece04SArınç ÜNAL mdio { 748c9aece04SArınç ÜNAL #address-cells = <1>; 749c9aece04SArınç ÜNAL #size-cells = <0>; 750c9aece04SArınç ÜNAL 751c9aece04SArınç ÜNAL /* External PHY */ 752c9aece04SArınç ÜNAL example7_ethphy7: ethernet-phy@7 { 753c9aece04SArınç ÜNAL reg = <7>; 754c9aece04SArınç ÜNAL phy-mode = "rgmii"; 755c9aece04SArınç ÜNAL }; 756c9aece04SArınç ÜNAL 7573737c6aaSArınç ÜNAL switch@1f { 758c9aece04SArınç ÜNAL compatible = "mediatek,mt7621"; 7593737c6aaSArınç ÜNAL reg = <0x1f>; 760c9aece04SArınç ÜNAL 761c9aece04SArınç ÜNAL mediatek,mcm; 762c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 763c9aece04SArınç ÜNAL reset-names = "mcm"; 764c9aece04SArınç ÜNAL 765c9aece04SArınç ÜNAL interrupt-controller; 766c9aece04SArınç ÜNAL #interrupt-cells = <1>; 767c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 768c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 769c9aece04SArınç ÜNAL 770c9aece04SArınç ÜNAL ethernet-ports { 771c9aece04SArınç ÜNAL #address-cells = <1>; 772c9aece04SArınç ÜNAL #size-cells = <0>; 773c9aece04SArınç ÜNAL 774c9aece04SArınç ÜNAL port@0 { 775c9aece04SArınç ÜNAL reg = <0>; 776c9aece04SArınç ÜNAL label = "lan1"; 777c9aece04SArınç ÜNAL }; 778c9aece04SArınç ÜNAL 779c9aece04SArınç ÜNAL port@1 { 780c9aece04SArınç ÜNAL reg = <1>; 781c9aece04SArınç ÜNAL label = "lan2"; 782c9aece04SArınç ÜNAL }; 783c9aece04SArınç ÜNAL 784c9aece04SArınç ÜNAL port@2 { 785c9aece04SArınç ÜNAL reg = <2>; 786c9aece04SArınç ÜNAL label = "lan3"; 787c9aece04SArınç ÜNAL }; 788c9aece04SArınç ÜNAL 789c9aece04SArınç ÜNAL port@3 { 790c9aece04SArınç ÜNAL reg = <3>; 791e0dda311SFrank Wunderlich label = "lan4"; 792e0dda311SFrank Wunderlich }; 793e0dda311SFrank Wunderlich 794c9aece04SArınç ÜNAL port@4 { 795c9aece04SArınç ÜNAL reg = <4>; 796c9aece04SArınç ÜNAL label = "wan"; 797c9aece04SArınç ÜNAL }; 798c9aece04SArınç ÜNAL 799e0dda311SFrank Wunderlich port@5 { 800e0dda311SFrank Wunderlich reg = <5>; 801c9aece04SArınç ÜNAL label = "extphy"; 802c9aece04SArınç ÜNAL phy-mode = "rgmii-txid"; 803c9aece04SArınç ÜNAL phy-handle = <&example7_ethphy7>; 804e0dda311SFrank Wunderlich }; 805e0dda311SFrank Wunderlich 806c9aece04SArınç ÜNAL port@6 { 807e0dda311SFrank Wunderlich reg = <6>; 808c9aece04SArınç ÜNAL ethernet = <&gmac0>; 809c9aece04SArınç ÜNAL phy-mode = "trgmii"; 810e0dda311SFrank Wunderlich 811e0dda311SFrank Wunderlich fixed-link { 812e0dda311SFrank Wunderlich speed = <1000>; 813e0dda311SFrank Wunderlich full-duplex; 814e0dda311SFrank Wunderlich pause; 815e0dda311SFrank Wunderlich }; 816e0dda311SFrank Wunderlich }; 817e0dda311SFrank Wunderlich }; 818e0dda311SFrank Wunderlich }; 819e0dda311SFrank Wunderlich }; 820e0dda311SFrank Wunderlich }; 821