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Searched full:reg_base (Results 1 – 25 of 364) sorted by relevance

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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
79 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
[all …]
/linux/drivers/gpio/
H A Dgpio-bcm-kona.c61 void __iomem *reg_base; member
76 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, in bcm_kona_gpio_write_lock_regs() argument
79 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); in bcm_kona_gpio_write_lock_regs()
80 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_write_lock_regs()
92 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
94 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
108 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
110 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
118 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir() local
121 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; in bcm_kona_gpio_get_dir()
[all …]
H A Dgpio-loongson-64bit.c36 void __iomem *reg_base; member
50 writeb(bval, lgpio->reg_base + lgpio->chip_data->conf_offset + pin); in loongson_commit_direction()
57 writeb(bval, lgpio->reg_base + lgpio->chip_data->out_offset + pin); in loongson_commit_level()
91 bval = readb(lgpio->reg_base + lgpio->chip_data->in_offset + pin); in loongson_gpio_get()
102 bval = readb(lgpio->reg_base + lgpio->chip_data->conf_offset + pin); in loongson_gpio_get_direction()
127 u = readl(lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4); in loongson_gpio_to_irq()
129 writel(u, lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4); in loongson_gpio_to_irq()
131 writeb(1, lgpio->reg_base + lgpio->chip_data->inten_offset + offset); in loongson_gpio_to_irq()
138 void __iomem *reg_base) in loongson_gpio_init() argument
143 lgpio->reg_base = reg_base; in loongson_gpio_init()
[all …]
H A Dgpio-loongson1.c21 void __iomem *reg_base; member
30 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset), in ls1x_gpio_request()
31 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_request()
43 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset), in ls1x_gpio_free()
44 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_free()
58 ls1x_gc->reg_base = devm_platform_ioremap_resource(pdev, 0); in ls1x_gpio_probe()
59 if (IS_ERR(ls1x_gc->reg_base)) in ls1x_gpio_probe()
60 return PTR_ERR(ls1x_gc->reg_base); in ls1x_gpio_probe()
62 ret = bgpio_init(&ls1x_gc->gc, dev, 4, ls1x_gc->reg_base + GPIO_DATA, in ls1x_gpio_probe()
63 ls1x_gc->reg_base + GPIO_OUTPUT, NULL, in ls1x_gpio_probe()
[all …]
/linux/drivers/spi/
H A Dspi-gxp.c43 void __iomem *reg_base; member
53 void __iomem *reg_base = spifi->reg_base; in gxp_spi_set_mode() local
55 value = readb(reg_base + OFFSET_SPIMCTRL); in gxp_spi_set_mode()
58 writeb(0x55, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
59 writeb(0xaa, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
64 writeb(value, reg_base + OFFSET_SPIMCTRL); in gxp_spi_set_mode()
71 void __iomem *reg_base = spifi->reg_base; in gxp_spi_read_reg() local
74 value = readl(reg_base + OFFSET_SPIMCFG); in gxp_spi_read_reg()
79 writel(value, reg_base + OFFSET_SPIMCFG); in gxp_spi_read_reg()
81 writel(0, reg_base + OFFSET_SPIADDR); in gxp_spi_read_reg()
[all …]
/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.c100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
105 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
113 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
119 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
132 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
177 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c47 void __iomem *reg_base; member
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
[all …]
/linux/drivers/misc/mchp_pci1xxxx/
H A Dmchp_pci1xxxx_gpio.c39 void __iomem *reg_base; member
51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_input()
83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_input()
93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; in pci1xxxx_gpio_get()
104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_output()
105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_output()
106 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
111 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
[all …]
/linux/drivers/irqchip/
H A Dirq-csky-apb-intc.c34 static void __iomem *reg_base; variable
60 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, in ck_set_gc() argument
66 gc->reg_base = reg_base; in ck_set_gc()
111 reg_base = of_iomap(node, 0); in ck_intc_init_comm()
112 if (!reg_base) { in ck_intc_init_comm()
153 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler()
158 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler()
175 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init()
176 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init()
181 writel(0x0, reg_base + GX_INTC_NMASK31_00); in gx_intc_init()
[all …]
H A Dirq-digicolor.c57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument
63 gc->reg_base = reg_base; in digicolor_set_gc()
74 void __iomem *reg_base; in digicolor_of_init() local
79 reg_base = of_iomap(node, 0); in digicolor_of_init()
80 if (!reg_base) { in digicolor_of_init()
86 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init()
87 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init()
112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init()
113 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.c130 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI); in ptp_reset_thresh()
134 writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_reset_thresh()
159 sec = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
160 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
161 sec1 = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
164 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
174 return readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_nsec()
258 writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_atomic_update()
259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_update()
261 ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_atomic_update()
[all …]
/linux/drivers/rtc/
H A Drtc-zynqmp.c52 void __iomem *reg_base; member
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
143 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
[all …]
/linux/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c24 static void __iomem *reg_base; variable
43 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in s5pv210_audss_clk_suspend()
53 writel(reg_save[i][1], reg_base + reg_save[i][0]); in s5pv210_audss_clk_resume()
72 reg_base = devm_platform_ioremap_resource(pdev, 0); in s5pv210_audss_clk_probe()
73 if (IS_ERR(reg_base)) in s5pv210_audss_clk_probe()
74 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
116 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
127 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in s5pv210_audss_clk_probe()
131 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in s5pv210_audss_clk_probe()
134 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
H A Dclk-exynos-audss.c21 static void __iomem *reg_base; variable
46 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in exynos_audss_clk_suspend()
56 writel(reg_save[i][1], reg_base + reg_save[i][0]); in exynos_audss_clk_resume()
138 reg_base = devm_platform_ioremap_resource(pdev, 0); in exynos_audss_clk_probe()
139 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
140 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
186 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
197 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
201 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in exynos_audss_clk_probe()
205 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in exynos_audss_clk_probe()
[all …]
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptpf_main.c26 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
28 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
33 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
40 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
52 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
54 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
57 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
64 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
75 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(0), in cptpf_enable_vf_flr_me_intrs()
79 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vf_flr_me_intrs()
[all …]
/linux/drivers/input/serio/
H A Dsun4i-ps2.c85 void __iomem *reg_base; member
107 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
108 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
130 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; in sun4i_ps2_interrupt()
134 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
135 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
151 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
158 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-pll.c34 void __iomem *reg_base; member
129 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1), in rockchip_rk3036_pll_wait_lock()
144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_get_params()
150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_get_params()
158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_get_params()
218 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params()
226 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params()
229 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
232 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
273 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable()
[all …]
/linux/drivers/input/keyboard/
H A Dnspire-keypad.c32 void __iomem *reg_base; member
61 int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask; in nspire_keypad_irq()
65 memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state)); in nspire_keypad_irq()
91 writel(0x3, keypad->reg_base + KEYPAD_INT); in nspire_keypad_irq()
121 writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); in nspire_keypad_open()
124 writel(val, keypad->reg_base + KEYPAD_CNTL); in nspire_keypad_open()
128 writel(keypad->int_mask, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_open()
138 writel(0, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_close()
140 writel(~0, keypad->reg_base + KEYPAD_INT); in nspire_keypad_close()
189 keypad->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in nspire_keypad_probe()
[all …]
/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cptvf_main.c349 vqx_ctl.u = readq(cptvf->reg_base + OTX_CPT_VQX_CTL(0)); in cptvf_write_vq_ctl()
351 writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0)); in cptvf_write_vq_ctl()
358 vqx_dbell.u = readq(cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); in otx_cptvf_write_vq_doorbell()
360 writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); in otx_cptvf_write_vq_doorbell()
367 vqx_inprg.u = readq(cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); in cptvf_write_vq_inprog()
369 writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); in cptvf_write_vq_inprog()
376 vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_numwait()
378 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_numwait()
385 vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_read_vq_done_numwait()
393 vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_timewait()
[all …]
/linux/drivers/fpga/
H A Daltera-pr-ip-core.c29 void __iomem *reg_base; member
39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state()
90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write()
123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write()
126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write()
129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write()
176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument
186 priv->reg_base = reg_base; in alt_pr_register()
[all …]
/linux/drivers/watchdog/
H A Dmeson_gxbb_wdt.c42 void __iomem *reg_base; member
55 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN, in meson_gxbb_wdt_start()
56 data->reg_base + GXBB_WDT_CTRL_REG); in meson_gxbb_wdt_start()
65 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN, in meson_gxbb_wdt_stop()
66 data->reg_base + GXBB_WDT_CTRL_REG); in meson_gxbb_wdt_stop()
75 writel(0, data->reg_base + GXBB_WDT_RSET_REG); in meson_gxbb_wdt_ping()
93 writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG); in meson_gxbb_wdt_set_timeout()
103 reg = readl(data->reg_base + GXBB_WDT_TCNT_REG); in meson_gxbb_wdt_get_timeleft()
172 data->reg_base = devm_platform_ioremap_resource(pdev, 0); in meson_gxbb_wdt_probe()
173 if (IS_ERR(data->reg_base)) in meson_gxbb_wdt_probe()
[all …]
/linux/drivers/video/fbdev/
H A Dpxa168fb.c287 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider()
297 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
322 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
334 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
344 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
357 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); in set_graphics_start()
369 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; in set_dumb_panel_control()
382 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); in set_dumb_panel_control()
395 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); in set_dumb_screen_dimensions()
418 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
[all …]
/linux/drivers/crypto/cavium/cpt/
H A Dcptvf_main.c366 vqx_ctl.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0)); in cptvf_write_vq_ctl()
368 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0), vqx_ctl.u); in cptvf_write_vq_ctl()
375 vqx_dbell.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_doorbell()
378 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DOORBELL(0, 0), in cptvf_write_vq_doorbell()
386 vqx_inprg.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0)); in cptvf_write_vq_inprog()
388 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0), vqx_inprg.u); in cptvf_write_vq_inprog()
395 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_done_numwait()
398 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), in cptvf_write_vq_done_numwait()
406 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_done_timewait()
409 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), in cptvf_write_vq_done_timewait()
[all …]
/linux/arch/powerpc/boot/
H A Dns16550.c31 static unsigned char *reg_base; variable
36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
43 out_8(reg_base, c); in ns16550_putc()
48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
49 return in_8(reg_base); in ns16550_getc()
54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
62 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) { in ns16550_console_init()
69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()
/linux/drivers/input/joystick/
H A Dn64joy.c51 u32 __iomem *reg_base; member
85 static void n64joy_write_reg(u32 __iomem *reg_base, const u8 reg, const u32 value) in n64joy_write_reg() argument
87 writel(value, reg_base + reg); in n64joy_write_reg()
90 static u32 n64joy_read_reg(u32 __iomem *reg_base, const u8 reg) in n64joy_read_reg() argument
92 return readl(reg_base + reg); in n64joy_read_reg()
95 static void n64joy_wait_si_dma(u32 __iomem *reg_base) in n64joy_wait_si_dma() argument
97 while (n64joy_read_reg(reg_base, SI_STATUS_REG) & in n64joy_wait_si_dma()
111 n64joy_wait_si_dma(priv->reg_base); in n64joy_exec_pif()
114 n64joy_write_reg(priv->reg_base, SI_DRAM_REG, virt_to_phys(in)); in n64joy_exec_pif()
116 n64joy_write_reg(priv->reg_base, SI_WRITE_REG, PIF_RAM); in n64joy_exec_pif()
[all …]

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