366 	vqx_ctl.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0));  in cptvf_write_vq_ctl()
368 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0), vqx_ctl.u);  in cptvf_write_vq_ctl()
375 	vqx_dbell.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_write_vq_doorbell()
378 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DOORBELL(0, 0),  in cptvf_write_vq_doorbell()
386 	vqx_inprg.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0));  in cptvf_write_vq_inprog()
388 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0), vqx_inprg.u);  in cptvf_write_vq_inprog()
395 	vqx_dwait.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_write_vq_done_numwait()
398 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0),  in cptvf_write_vq_done_numwait()
406 	vqx_dwait.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_write_vq_done_timewait()
409 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0),  in cptvf_write_vq_done_timewait()
417 	vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_enable_swerr_interrupts()
421 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),  in cptvf_enable_swerr_interrupts()
429 	vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_enable_mbox_interrupts()
433 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),  in cptvf_enable_mbox_interrupts()
441 	vqx_done_ena.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_enable_done_interrupts()
445 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ENA_W1S(0, 0),  in cptvf_enable_done_interrupts()
453 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_clear_dovf_intr()
457 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),  in cptvf_clear_dovf_intr()
465 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_clear_irde_intr()
469 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),  in cptvf_clear_irde_intr()
477 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_clear_nwrp_intr()
481 	cpt_write_csr64(cptvf->reg_base,  in cptvf_clear_nwrp_intr()
489 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_clear_mbox_intr()
493 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),  in cptvf_clear_mbox_intr()
501 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_clear_swerr_intr()
505 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),  in cptvf_clear_swerr_intr()
511 	return cpt_read_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0));  in cptvf_read_vf_misc_intr_status()
569 	vqx_done.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_DONE(0, 0));  in cptvf_read_vq_done_count()
578 	vqx_dack_cnt.u = cpt_read_csr64(cptvf->reg_base,  in cptvf_write_vq_done_ack()
581 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ACK(0, 0),  in cptvf_write_vq_done_ack()
635 	cpt_write_csr64(cptvf->reg_base, CPTX_VQX_SADDR(0, 0), vqx_saddr.u);  in cptvf_write_vq_saddr()
694 	cptvf->reg_base = pcim_iomap(pdev, 0, 0);  in cptvf_probe()
695 	if (!cptvf->reg_base) {  in cptvf_probe()