61 	void __iomem *reg_base;  member
76 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,  in bcm_kona_gpio_write_lock_regs()  argument
79 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);  in bcm_kona_gpio_write_lock_regs()
80 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_write_lock_regs()
92 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_lock_gpio()
94 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_lock_gpio()
108 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_unlock_gpio()
110 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_unlock_gpio()
118 	void __iomem *reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get_dir()  local
121 	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;  in bcm_kona_gpio_get_dir()
128 	void __iomem *reg_base;  in bcm_kona_gpio_set()  local
135 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set()
144 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_set()
146 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_set()
155 	void __iomem *reg_base;  in bcm_kona_gpio_get()  local
162 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get()
171 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_get()
197 	void __iomem *reg_base;  in bcm_kona_gpio_direction_input()  local
202 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_input()
205 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
208 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
219 	void __iomem *reg_base;  in bcm_kona_gpio_direction_output()  local
226 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_output()
229 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
232 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
235 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
237 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
258 	void __iomem *reg_base;  in bcm_kona_gpio_set_debounce()  local
263 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set_debounce()
285 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
296 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
333 	void __iomem *reg_base;  in bcm_kona_gpio_irq_ack()  local
341 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_ack()
344 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
346 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
354 	void __iomem *reg_base;  in bcm_kona_gpio_irq_mask()  local
362 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_mask()
365 	val = readl(reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
367 	writel(val, reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
376 	void __iomem *reg_base;  in bcm_kona_gpio_irq_unmask()  local
384 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_unmask()
387 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
389 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
398 	void __iomem *reg_base;  in bcm_kona_gpio_irq_set_type()  local
405 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_set_type()
430 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
433 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
442 	void __iomem *reg_base;  in bcm_kona_gpio_irq_handler()  local
455 	reg_base = bank->kona_gpio->reg_base;  in bcm_kona_gpio_irq_handler()
458 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &  in bcm_kona_gpio_irq_handler()
459 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {  in bcm_kona_gpio_irq_handler()
466 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |  in bcm_kona_gpio_irq_handler()
467 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_handler()
542 	void __iomem *reg_base;  in bcm_kona_gpio_reset()  local
545 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_reset()
549 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);  in bcm_kona_gpio_reset()
550 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));  in bcm_kona_gpio_reset()
551 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));  in bcm_kona_gpio_reset()
553 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);  in bcm_kona_gpio_reset()
605 	kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);  in bcm_kona_gpio_probe()
606 	if (IS_ERR(kona_gpio->reg_base)) {  in bcm_kona_gpio_probe()
607 		ret = PTR_ERR(kona_gpio->reg_base);  in bcm_kona_gpio_probe()