1473f01f7SAlan Tull // SPDX-License-Identifier: GPL-2.0
2d201cc17SMatthew Gerlach /*
3d201cc17SMatthew Gerlach * Driver for Altera Partial Reconfiguration IP Core
4d201cc17SMatthew Gerlach *
5d201cc17SMatthew Gerlach * Copyright (C) 2016-2017 Intel Corporation
6d201cc17SMatthew Gerlach *
7d201cc17SMatthew Gerlach * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
8d201cc17SMatthew Gerlach * by Alan Tull <atull@opensource.altera.com>
9d201cc17SMatthew Gerlach */
10d201cc17SMatthew Gerlach #include <linux/delay.h>
11d201cc17SMatthew Gerlach #include <linux/fpga/altera-pr-ip-core.h>
12d201cc17SMatthew Gerlach #include <linux/fpga/fpga-mgr.h>
13d201cc17SMatthew Gerlach #include <linux/module.h>
14d201cc17SMatthew Gerlach
15d201cc17SMatthew Gerlach #define ALT_PR_DATA_OFST 0x00
16d201cc17SMatthew Gerlach #define ALT_PR_CSR_OFST 0x04
17d201cc17SMatthew Gerlach
18d201cc17SMatthew Gerlach #define ALT_PR_CSR_PR_START BIT(0)
19d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_SFT 2
20d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_MSK (7 << ALT_PR_CSR_STATUS_SFT)
21d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_NRESET (0 << ALT_PR_CSR_STATUS_SFT)
22d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_PR_ERR (1 << ALT_PR_CSR_STATUS_SFT)
23d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_CRC_ERR (2 << ALT_PR_CSR_STATUS_SFT)
24d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_BAD_BITS (3 << ALT_PR_CSR_STATUS_SFT)
25d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_PR_IN_PROG (4 << ALT_PR_CSR_STATUS_SFT)
26d201cc17SMatthew Gerlach #define ALT_PR_CSR_STATUS_PR_SUCCESS (5 << ALT_PR_CSR_STATUS_SFT)
27d201cc17SMatthew Gerlach
28d201cc17SMatthew Gerlach struct alt_pr_priv {
29d201cc17SMatthew Gerlach void __iomem *reg_base;
30d201cc17SMatthew Gerlach };
31d201cc17SMatthew Gerlach
alt_pr_fpga_state(struct fpga_manager * mgr)32d201cc17SMatthew Gerlach static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
33d201cc17SMatthew Gerlach {
34d201cc17SMatthew Gerlach struct alt_pr_priv *priv = mgr->priv;
35d201cc17SMatthew Gerlach const char *err = "unknown";
36d201cc17SMatthew Gerlach enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
37d201cc17SMatthew Gerlach u32 val;
38d201cc17SMatthew Gerlach
39d201cc17SMatthew Gerlach val = readl(priv->reg_base + ALT_PR_CSR_OFST);
40d201cc17SMatthew Gerlach
41d201cc17SMatthew Gerlach val &= ALT_PR_CSR_STATUS_MSK;
42d201cc17SMatthew Gerlach
43d201cc17SMatthew Gerlach switch (val) {
44d201cc17SMatthew Gerlach case ALT_PR_CSR_STATUS_NRESET:
45d201cc17SMatthew Gerlach return FPGA_MGR_STATE_RESET;
46d201cc17SMatthew Gerlach
47d201cc17SMatthew Gerlach case ALT_PR_CSR_STATUS_PR_ERR:
48d201cc17SMatthew Gerlach err = "pr error";
49d201cc17SMatthew Gerlach ret = FPGA_MGR_STATE_WRITE_ERR;
50d201cc17SMatthew Gerlach break;
51d201cc17SMatthew Gerlach
52d201cc17SMatthew Gerlach case ALT_PR_CSR_STATUS_CRC_ERR:
53d201cc17SMatthew Gerlach err = "crc error";
54d201cc17SMatthew Gerlach ret = FPGA_MGR_STATE_WRITE_ERR;
55d201cc17SMatthew Gerlach break;
56d201cc17SMatthew Gerlach
57d201cc17SMatthew Gerlach case ALT_PR_CSR_STATUS_BAD_BITS:
58d201cc17SMatthew Gerlach err = "bad bits";
59d201cc17SMatthew Gerlach ret = FPGA_MGR_STATE_WRITE_ERR;
60d201cc17SMatthew Gerlach break;
61d201cc17SMatthew Gerlach
62d201cc17SMatthew Gerlach case ALT_PR_CSR_STATUS_PR_IN_PROG:
63d201cc17SMatthew Gerlach return FPGA_MGR_STATE_WRITE;
64d201cc17SMatthew Gerlach
65d201cc17SMatthew Gerlach case ALT_PR_CSR_STATUS_PR_SUCCESS:
66d201cc17SMatthew Gerlach return FPGA_MGR_STATE_OPERATING;
67d201cc17SMatthew Gerlach
68d201cc17SMatthew Gerlach default:
69d201cc17SMatthew Gerlach break;
70d201cc17SMatthew Gerlach }
71d201cc17SMatthew Gerlach
72d201cc17SMatthew Gerlach dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
73d201cc17SMatthew Gerlach val, err, __func__);
74d201cc17SMatthew Gerlach return ret;
75d201cc17SMatthew Gerlach }
76d201cc17SMatthew Gerlach
alt_pr_fpga_write_init(struct fpga_manager * mgr,struct fpga_image_info * info,const char * buf,size_t count)77d201cc17SMatthew Gerlach static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
78d201cc17SMatthew Gerlach struct fpga_image_info *info,
79d201cc17SMatthew Gerlach const char *buf, size_t count)
80d201cc17SMatthew Gerlach {
81d201cc17SMatthew Gerlach struct alt_pr_priv *priv = mgr->priv;
82d201cc17SMatthew Gerlach u32 val;
83d201cc17SMatthew Gerlach
84d201cc17SMatthew Gerlach if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
85d201cc17SMatthew Gerlach dev_err(&mgr->dev, "%s Partial Reconfiguration flag not set\n",
86d201cc17SMatthew Gerlach __func__);
87d201cc17SMatthew Gerlach return -EINVAL;
88d201cc17SMatthew Gerlach }
89d201cc17SMatthew Gerlach
90d201cc17SMatthew Gerlach val = readl(priv->reg_base + ALT_PR_CSR_OFST);
91d201cc17SMatthew Gerlach
92d201cc17SMatthew Gerlach if (val & ALT_PR_CSR_PR_START) {
93d201cc17SMatthew Gerlach dev_err(&mgr->dev,
94d201cc17SMatthew Gerlach "%s Partial Reconfiguration already started\n",
95d201cc17SMatthew Gerlach __func__);
96d201cc17SMatthew Gerlach return -EINVAL;
97d201cc17SMatthew Gerlach }
98d201cc17SMatthew Gerlach
99d201cc17SMatthew Gerlach writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
100d201cc17SMatthew Gerlach
101d201cc17SMatthew Gerlach return 0;
102d201cc17SMatthew Gerlach }
103d201cc17SMatthew Gerlach
alt_pr_fpga_write(struct fpga_manager * mgr,const char * buf,size_t count)104d201cc17SMatthew Gerlach static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
105d201cc17SMatthew Gerlach size_t count)
106d201cc17SMatthew Gerlach {
107d201cc17SMatthew Gerlach struct alt_pr_priv *priv = mgr->priv;
108d201cc17SMatthew Gerlach u32 *buffer_32 = (u32 *)buf;
109d201cc17SMatthew Gerlach size_t i = 0;
110d201cc17SMatthew Gerlach
111*2df84a75SMarco Pagani if (!count)
112d201cc17SMatthew Gerlach return -EINVAL;
113d201cc17SMatthew Gerlach
114d201cc17SMatthew Gerlach /* Write out the complete 32-bit chunks */
115d201cc17SMatthew Gerlach while (count >= sizeof(u32)) {
116d201cc17SMatthew Gerlach writel(buffer_32[i++], priv->reg_base);
117d201cc17SMatthew Gerlach count -= sizeof(u32);
118d201cc17SMatthew Gerlach }
119d201cc17SMatthew Gerlach
120d201cc17SMatthew Gerlach /* Write out remaining non 32-bit chunks */
121d201cc17SMatthew Gerlach switch (count) {
122d201cc17SMatthew Gerlach case 3:
123d201cc17SMatthew Gerlach writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
124d201cc17SMatthew Gerlach break;
125d201cc17SMatthew Gerlach case 2:
126d201cc17SMatthew Gerlach writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
127d201cc17SMatthew Gerlach break;
128d201cc17SMatthew Gerlach case 1:
129d201cc17SMatthew Gerlach writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
130d201cc17SMatthew Gerlach break;
131d201cc17SMatthew Gerlach case 0:
132d201cc17SMatthew Gerlach break;
133d201cc17SMatthew Gerlach default:
134d201cc17SMatthew Gerlach /* This will never happen */
135d201cc17SMatthew Gerlach return -EFAULT;
136d201cc17SMatthew Gerlach }
137d201cc17SMatthew Gerlach
138d201cc17SMatthew Gerlach if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)
139d201cc17SMatthew Gerlach return -EIO;
140d201cc17SMatthew Gerlach
141d201cc17SMatthew Gerlach return 0;
142d201cc17SMatthew Gerlach }
143d201cc17SMatthew Gerlach
alt_pr_fpga_write_complete(struct fpga_manager * mgr,struct fpga_image_info * info)144d201cc17SMatthew Gerlach static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
145d201cc17SMatthew Gerlach struct fpga_image_info *info)
146d201cc17SMatthew Gerlach {
147d201cc17SMatthew Gerlach u32 i = 0;
148d201cc17SMatthew Gerlach
149d201cc17SMatthew Gerlach do {
150d201cc17SMatthew Gerlach switch (alt_pr_fpga_state(mgr)) {
151d201cc17SMatthew Gerlach case FPGA_MGR_STATE_WRITE_ERR:
152d201cc17SMatthew Gerlach return -EIO;
153d201cc17SMatthew Gerlach
154d201cc17SMatthew Gerlach case FPGA_MGR_STATE_OPERATING:
155d201cc17SMatthew Gerlach dev_info(&mgr->dev,
156d201cc17SMatthew Gerlach "successful partial reconfiguration\n");
157d201cc17SMatthew Gerlach return 0;
158d201cc17SMatthew Gerlach
159d201cc17SMatthew Gerlach default:
160d201cc17SMatthew Gerlach break;
161d201cc17SMatthew Gerlach }
162d201cc17SMatthew Gerlach udelay(1);
163d201cc17SMatthew Gerlach } while (info->config_complete_timeout_us > i++);
164d201cc17SMatthew Gerlach
165d201cc17SMatthew Gerlach dev_err(&mgr->dev, "timed out waiting for write to complete\n");
166d201cc17SMatthew Gerlach return -ETIMEDOUT;
167d201cc17SMatthew Gerlach }
168d201cc17SMatthew Gerlach
169d201cc17SMatthew Gerlach static const struct fpga_manager_ops alt_pr_ops = {
170d201cc17SMatthew Gerlach .state = alt_pr_fpga_state,
171d201cc17SMatthew Gerlach .write_init = alt_pr_fpga_write_init,
172d201cc17SMatthew Gerlach .write = alt_pr_fpga_write,
173d201cc17SMatthew Gerlach .write_complete = alt_pr_fpga_write_complete,
174d201cc17SMatthew Gerlach };
175d201cc17SMatthew Gerlach
alt_pr_register(struct device * dev,void __iomem * reg_base)176d201cc17SMatthew Gerlach int alt_pr_register(struct device *dev, void __iomem *reg_base)
177d201cc17SMatthew Gerlach {
178d201cc17SMatthew Gerlach struct alt_pr_priv *priv;
1797085e2a9SAlan Tull struct fpga_manager *mgr;
180d201cc17SMatthew Gerlach u32 val;
181d201cc17SMatthew Gerlach
182d201cc17SMatthew Gerlach priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
183d201cc17SMatthew Gerlach if (!priv)
184d201cc17SMatthew Gerlach return -ENOMEM;
185d201cc17SMatthew Gerlach
186d201cc17SMatthew Gerlach priv->reg_base = reg_base;
187d201cc17SMatthew Gerlach
188d201cc17SMatthew Gerlach val = readl(priv->reg_base + ALT_PR_CSR_OFST);
189d201cc17SMatthew Gerlach
190d201cc17SMatthew Gerlach dev_dbg(dev, "%s status=%d start=%d\n", __func__,
191d201cc17SMatthew Gerlach (val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
192d201cc17SMatthew Gerlach (int)(val & ALT_PR_CSR_PR_START));
193d201cc17SMatthew Gerlach
1944ba0b2c2SRuss Weight mgr = devm_fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);
1954ba0b2c2SRuss Weight return PTR_ERR_OR_ZERO(mgr);
196d201cc17SMatthew Gerlach }
197d201cc17SMatthew Gerlach EXPORT_SYMBOL_GPL(alt_pr_register);
198d201cc17SMatthew Gerlach
199d201cc17SMatthew Gerlach MODULE_AUTHOR("Matthew Gerlach <matthew.gerlach@linux.intel.com>");
200d201cc17SMatthew Gerlach MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
201d201cc17SMatthew Gerlach MODULE_LICENSE("GPL v2");
202