349 	vqx_ctl.u = readq(cptvf->reg_base + OTX_CPT_VQX_CTL(0));  in cptvf_write_vq_ctl()
351 	writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0));  in cptvf_write_vq_ctl()
358 	vqx_dbell.u = readq(cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0));  in otx_cptvf_write_vq_doorbell()
360 	writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0));  in otx_cptvf_write_vq_doorbell()
367 	vqx_inprg.u = readq(cptvf->reg_base + OTX_CPT_VQX_INPROG(0));  in cptvf_write_vq_inprog()
369 	writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0));  in cptvf_write_vq_inprog()
376 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_write_vq_done_numwait()
378 	writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_write_vq_done_numwait()
385 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_read_vq_done_numwait()
393 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_write_vq_done_timewait()
395 	writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_write_vq_done_timewait()
403 	vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));  in cptvf_read_vq_done_timewait()
411 	vqx_misc_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));  in cptvf_enable_swerr_interrupts()
414 	writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));  in cptvf_enable_swerr_interrupts()
421 	vqx_misc_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));  in cptvf_enable_mbox_interrupts()
424 	writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));  in cptvf_enable_mbox_interrupts()
431 	vqx_done_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0));  in cptvf_enable_done_interrupts()
434 	writeq(vqx_done_ena.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0));  in cptvf_enable_done_interrupts()
441 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_dovf_intr()
444 	writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_dovf_intr()
451 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_irde_intr()
454 	writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_irde_intr()
461 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_nwrp_intr()
464 	writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_nwrp_intr()
471 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_mbox_intr()
474 	writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_mbox_intr()
481 	vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_swerr_intr()
484 	writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_clear_swerr_intr()
489 	return readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));  in cptvf_read_vf_misc_intr_status()
552 	vqx_done.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE(0));  in cptvf_read_vq_done_count()
561 	vqx_dack_cnt.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_ACK(0));  in cptvf_write_vq_done_ack()
563 	writeq(vqx_dack_cnt.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ACK(0));  in cptvf_write_vq_done_ack()
619 	writeq(vqx_saddr.u, cptvf->reg_base + OTX_CPT_VQX_SADDR(0));  in cptvf_write_vq_saddr()
811 	cptvf->reg_base = pci_iomap(pdev, OTX_CPT_VF_PCI_CFG_BAR, 0);  in otx_cptvf_probe()
812 	if (!cptvf->reg_base) {  in otx_cptvf_probe()
918 	pci_iounmap(pdev, cptvf->reg_base);  in otx_cptvf_probe()
950 		pci_iounmap(pdev, cptvf->reg_base);  in otx_cptvf_remove()