Lines Matching full:reg_base
39 void __iomem *reg_base; member
52 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
56 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
83 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_input()
84 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_input()
94 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; in pci1xxxx_gpio_get()
105 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_output()
106 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_output()
107 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
112 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
125 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val); in pci1xxxx_gpio_set()
139 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
142 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
145 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
146 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
149 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
152 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
171 writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio)); in pci1xxxx_gpio_irq_ack()
185 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set); in pci1xxxx_gpio_irq_set_mask()
209 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
211 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), in pci1xxxx_gpio_set_type()
215 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
220 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
222 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
226 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
231 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), in pci1xxxx_gpio_set_type()
233 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), in pci1xxxx_gpio_set_type()
235 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
241 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), in pci1xxxx_gpio_set_type()
243 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), in pci1xxxx_gpio_set_type()
245 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
251 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true); in pci1xxxx_gpio_set_type()
268 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true); in pci1xxxx_gpio_irq_handler()
272 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); in pci1xxxx_gpio_irq_handler()
282 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); in pci1xxxx_gpio_irq_handler()
291 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false); in pci1xxxx_gpio_irq_handler()
313 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend()
315 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend()
317 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true); in pci1xxxx_gpio_suspend()
329 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_resume()
331 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_resume()
333 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false); in pci1xxxx_gpio_resume()
404 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800); in pci1xxxx_gpio_probe()
405 if (!priv->reg_base) in pci1xxxx_gpio_probe()
408 writel(0x0264, (priv->reg_base + 0x400 + 0xF0)); in pci1xxxx_gpio_probe()