287 	writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV);  in set_clock_divider()
297 	x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);  in set_dma_control0()
322 	writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);  in set_dma_control0()
334 	x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1);  in set_dma_control1()
344 	writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);  in set_dma_control1()
357 	writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0);  in set_graphics_start()
369 	x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001;  in set_dumb_panel_control()
382 	writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL);  in set_dumb_panel_control()
395 	writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL);  in set_dumb_screen_dimensions()
418 	x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
419 	writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
425 		fbi->reg_base + LCD_SPU_V_H_ACTIVE);  in pxa168fb_set_par()
442 	x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH);  in pxa168fb_set_par()
444 	writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH);  in pxa168fb_set_par()
446 		fbi->reg_base + LCD_SPU_GRA_HPXL_VLN);  in pxa168fb_set_par()
448 		fbi->reg_base + LCD_SPU_GZM_HPXL_VLN);  in pxa168fb_set_par()
457 			fbi->reg_base + LCD_SPU_H_PORCH);  in pxa168fb_set_par()
459 			fbi->reg_base + LCD_SPU_V_PORCH);  in pxa168fb_set_par()
464 	x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
465 	writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
504 		writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT);  in pxa168fb_setcolreg()
505 		writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL);  in pxa168fb_setcolreg()
532 	u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR);  in pxa168fb_handle_irq()
537 			fbi->reg_base + SPU_IRQ_ISR);  in pxa168fb_handle_irq()
656 	fbi->reg_base = devm_ioremap(&pdev->dev, res->start,  in pxa168fb_probe()
658 	if (fbi->reg_base == NULL) {  in pxa168fb_probe()
707 	writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR);  in pxa168fb_probe()
708 	writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL);  in pxa168fb_probe()
709 	writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1);  in pxa168fb_probe()
710 	writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN);  in pxa168fb_probe()
711 	writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0);  in pxa168fb_probe()
713 		fbi->reg_base + LCD_SPU_SRAM_PARA1);  in pxa168fb_probe()
737 	writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA);  in pxa168fb_probe()
776 	data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);  in pxa168fb_remove()
778 	writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0);  in pxa168fb_remove()
784 	writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA);  in pxa168fb_remove()