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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
12 compatible = "renesas,r9a07g044";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
[all …]
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Drenesas,rzg2l-du.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
20 - enum:
21 - renesas,r9a07g043u-du # RZ/G2UL
22 - renesas,r9a07g044-du # RZ/G2{L,LC}
23 - items:
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Drenesas,sci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a07g043-sci # RZ/G2UL and RZ/Five
21 - renesas,r9a07g044-sci # RZ/G2{L,LC}
22 - renesas,r9a07g054-sci # RZ/V2L
[all …]
H A Drenesas,scif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,scif-r7s72100 # RZ/A1H
18 - const: renesas,scif # generic SCIF compatible UART
20 - items:
21 - enum:
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Drenesas,rzg2l-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
15 color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and
16 parallel (including ITU-R BT.656) input are provided as the image sensor interface.
21 - enum:
22 - renesas,r9a07g043-cru # RZ/G2UL
23 - renesas,r9a07g044-cru # RZ/G2{L,LC}
[all …]
H A Drenesas,rzg2l-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
21 - enum:
22 - renesas,r9a07g043-csi2 # RZ/G2UL
[all …]
H A Drenesas,vsp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
20 - enum:
21 - renesas,r9a07g044-vsp2 # RZ/G2L
22 - renesas,vsp1 # R-Car Gen2 and RZ/G1
23 - renesas,vsp2 # R-Car Gen3 and RZ/G2
[all …]
H A Drenesas,fcp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Frame Compression Processor (FCP)
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 R-Car Gen3 and RZ/G2 SoCs. It provides data compression and decompression,
25 - enum:
26 - renesas,fcpv # FCP for VSP
27 - renesas,fcpf # FCP for FDP
28 - items:
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
33 - description: Sequence operation channel 0 interrupt
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Drenesas,rzg2l-usbphy-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
19 - enum:
20 - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
21 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
22 - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
23 - const: renesas,rzg2l-usbphy-ctrl
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Drzg2l-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/rzg2l-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Biju Das <biju.das.jz@bp.renesas.com>
16 $ref: thermal-sensor.yaml#
21 - enum:
22 - renesas,r9a07g043-tsu # RZ/G2UL and RZ/Five
23 - renesas,r9a07g044-tsu # RZ/G2{L,LC}
24 - renesas,r9a07g054-tsu # RZ/V2L
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Drenesas,rzg2l-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
16 stored in a 32-bit data register corresponding to each channel.
21 - enum:
22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-poeg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
17 * Output-disable request from the GPT.
26 - enum:
27 - renesas,r9a07g044-poeg # RZ/G2{L,LC}
28 - renesas,r9a07g054-poeg # RZ/V2L
29 - const: renesas,rzg2l-poeg
[all …]
H A Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
[all …]
/linux/drivers/clk/renesas/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o
5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzg2l-cpg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
27 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
28 - renesas,r9a07g044-cpg # RZ/G2{L,LC}
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Drenesas,rz-ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 - $ref: dai-common.yaml#
18 - enum:
19 - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five
20 - renesas,r9a07g044-ssi # RZ/G2{L,LC}
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,rzg2l-irqc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,rspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,rspi-sh7757 # SH7757
18 - const: renesas,rspi # Legacy SH
20 - items:
21 - enum:
[all …]
/linux/include/dt-bindings/clock/
H A Dr9a07g044-cpg.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* R9A07G044 CPG Core Clocks */
35 /* R9A07G044 Module Clocks */
134 /* R9A07G044 Resets */
/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32-bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max
16 - Pulse input 3 lines
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - enum:
17 - renesas,usb2-phy-r8a77470 # RZ/G1C
18 - renesas,usb2-phy-r9a08g045 # RZ/G3S
[all …]
/linux/Documentation/devicetree/bindings/net/can/
H A Drenesas,rcar-canfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN FD Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
15 - items:
16 - enum:
17 - renesas,r8a774a1-canfd # RZ/G2M
18 - renesas,r8a774b1-canfd # RZ/G2N
[all …]

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