1a1800417SLad Prabhakar# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2a1800417SLad Prabhakar# Copyright (C) 2022 Renesas Electronics Corp. 3a1800417SLad Prabhakar%YAML 1.2 4a1800417SLad Prabhakar--- 5a1800417SLad Prabhakar$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# 6a1800417SLad Prabhakar$schema: http://devicetree.org/meta-schemas/core.yaml# 7a1800417SLad Prabhakar 8a1800417SLad Prabhakartitle: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing 9a1800417SLad Prabhakar 10a1800417SLad Prabhakarmaintainers: 11a1800417SLad Prabhakar - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12a1800417SLad Prabhakar 13a1800417SLad Prabhakardescription: 14a1800417SLad Prabhakar The CRU image processing module is a data conversion module equipped with pixel 15a1800417SLad Prabhakar color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and 16a1800417SLad Prabhakar parallel (including ITU-R BT.656) input are provided as the image sensor interface. 17a1800417SLad Prabhakar 18a1800417SLad Prabhakarproperties: 19a1800417SLad Prabhakar compatible: 20a1800417SLad Prabhakar items: 21a1800417SLad Prabhakar - enum: 22*83138f8fSBiju Das - renesas,r9a07g043-cru # RZ/G2UL 23a1800417SLad Prabhakar - renesas,r9a07g044-cru # RZ/G2{L,LC} 24a1800417SLad Prabhakar - renesas,r9a07g054-cru # RZ/V2L 25a1800417SLad Prabhakar - const: renesas,rzg2l-cru 26a1800417SLad Prabhakar 27a1800417SLad Prabhakar reg: 28a1800417SLad Prabhakar maxItems: 1 29a1800417SLad Prabhakar 30a1800417SLad Prabhakar interrupts: 31a1800417SLad Prabhakar maxItems: 3 32a1800417SLad Prabhakar 33a1800417SLad Prabhakar interrupt-names: 34a1800417SLad Prabhakar items: 35a1800417SLad Prabhakar - const: image_conv 36a1800417SLad Prabhakar - const: image_conv_err 37a1800417SLad Prabhakar - const: axi_mst_err 38a1800417SLad Prabhakar 39a1800417SLad Prabhakar clocks: 40a1800417SLad Prabhakar items: 41a1800417SLad Prabhakar - description: CRU Main clock 42a1800417SLad Prabhakar - description: CRU Register access clock 43a1800417SLad Prabhakar - description: CRU image transfer clock 44a1800417SLad Prabhakar 45a1800417SLad Prabhakar clock-names: 46a1800417SLad Prabhakar items: 47a1800417SLad Prabhakar - const: video 48a1800417SLad Prabhakar - const: apb 49a1800417SLad Prabhakar - const: axi 50a1800417SLad Prabhakar 51a1800417SLad Prabhakar power-domains: 52a1800417SLad Prabhakar maxItems: 1 53a1800417SLad Prabhakar 54a1800417SLad Prabhakar resets: 55a1800417SLad Prabhakar items: 56a1800417SLad Prabhakar - description: CRU_PRESETN reset terminal 57a1800417SLad Prabhakar - description: CRU_ARESETN reset terminal 58a1800417SLad Prabhakar 59a1800417SLad Prabhakar reset-names: 60a1800417SLad Prabhakar items: 61a1800417SLad Prabhakar - const: presetn 62a1800417SLad Prabhakar - const: aresetn 63a1800417SLad Prabhakar 64a1800417SLad Prabhakar ports: 65a1800417SLad Prabhakar $ref: /schemas/graph.yaml#/properties/ports 66a1800417SLad Prabhakar 67a1800417SLad Prabhakar properties: 68a1800417SLad Prabhakar port@0: 69a1800417SLad Prabhakar $ref: /schemas/graph.yaml#/$defs/port-base 70a1800417SLad Prabhakar unevaluatedProperties: false 71a1800417SLad Prabhakar description: 72a1800417SLad Prabhakar Input port node, single endpoint describing a parallel input source. 73a1800417SLad Prabhakar 74a1800417SLad Prabhakar properties: 75a1800417SLad Prabhakar endpoint: 76a1800417SLad Prabhakar $ref: video-interfaces.yaml# 77a1800417SLad Prabhakar unevaluatedProperties: false 78a1800417SLad Prabhakar 79a1800417SLad Prabhakar properties: 80a1800417SLad Prabhakar hsync-active: true 81a1800417SLad Prabhakar vsync-active: true 82a1800417SLad Prabhakar bus-width: true 83a1800417SLad Prabhakar data-shift: true 84a1800417SLad Prabhakar 85a1800417SLad Prabhakar port@1: 86a1800417SLad Prabhakar $ref: /schemas/graph.yaml#/properties/port 87a1800417SLad Prabhakar description: 88a1800417SLad Prabhakar Input port node, describing the Image Processing module connected to the 89a1800417SLad Prabhakar CSI-2 receiver. 90a1800417SLad Prabhakar 91a1800417SLad Prabhakarrequired: 92a1800417SLad Prabhakar - compatible 93a1800417SLad Prabhakar - reg 94a1800417SLad Prabhakar - interrupts 95a1800417SLad Prabhakar - interrupt-names 96a1800417SLad Prabhakar - clocks 97a1800417SLad Prabhakar - clock-names 98a1800417SLad Prabhakar - resets 99a1800417SLad Prabhakar - reset-names 100a1800417SLad Prabhakar - power-domains 101a1800417SLad Prabhakar 102*83138f8fSBiju DasallOf: 103*83138f8fSBiju Das - if: 104*83138f8fSBiju Das properties: 105*83138f8fSBiju Das compatible: 106*83138f8fSBiju Das contains: 107*83138f8fSBiju Das enum: 108*83138f8fSBiju Das - renesas,r9a07g044-cru 109*83138f8fSBiju Das - renesas,r9a07g054-cru 110*83138f8fSBiju Das then: 111*83138f8fSBiju Das properties: 112*83138f8fSBiju Das ports: 113*83138f8fSBiju Das required: 114*83138f8fSBiju Das - port@0 115*83138f8fSBiju Das - port@1 116*83138f8fSBiju Das 117*83138f8fSBiju Das - if: 118*83138f8fSBiju Das properties: 119*83138f8fSBiju Das compatible: 120*83138f8fSBiju Das contains: 121*83138f8fSBiju Das enum: 122*83138f8fSBiju Das - renesas,r9a07g043-cru 123*83138f8fSBiju Das then: 124*83138f8fSBiju Das properties: 125*83138f8fSBiju Das ports: 126*83138f8fSBiju Das properties: 127*83138f8fSBiju Das port@0: false 128*83138f8fSBiju Das 129*83138f8fSBiju Das required: 130*83138f8fSBiju Das - port@1 131*83138f8fSBiju Das 132a1800417SLad PrabhakaradditionalProperties: false 133a1800417SLad Prabhakar 134a1800417SLad Prabhakarexamples: 135a1800417SLad Prabhakar # Device node example with CSI-2 136a1800417SLad Prabhakar - | 137a1800417SLad Prabhakar #include <dt-bindings/clock/r9a07g044-cpg.h> 138a1800417SLad Prabhakar #include <dt-bindings/interrupt-controller/arm-gic.h> 139a1800417SLad Prabhakar 140a1800417SLad Prabhakar cru: video@10830000 { 141a1800417SLad Prabhakar compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; 142a1800417SLad Prabhakar reg = <0x10830000 0x400>; 143a1800417SLad Prabhakar interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 144a1800417SLad Prabhakar <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 145a1800417SLad Prabhakar <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 146a1800417SLad Prabhakar interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; 147a1800417SLad Prabhakar clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, 148a1800417SLad Prabhakar <&cpg CPG_MOD R9A07G044_CRU_PCLK>, 149a1800417SLad Prabhakar <&cpg CPG_MOD R9A07G044_CRU_ACLK>; 150a1800417SLad Prabhakar clock-names = "video", "apb", "axi"; 151a1800417SLad Prabhakar power-domains = <&cpg>; 152a1800417SLad Prabhakar resets = <&cpg R9A07G044_CRU_PRESETN>, 153a1800417SLad Prabhakar <&cpg R9A07G044_CRU_ARESETN>; 154a1800417SLad Prabhakar reset-names = "presetn", "aresetn"; 155a1800417SLad Prabhakar 156a1800417SLad Prabhakar ports { 157a1800417SLad Prabhakar #address-cells = <1>; 158a1800417SLad Prabhakar #size-cells = <0>; 159a1800417SLad Prabhakar 160a1800417SLad Prabhakar port@0 { 161a1800417SLad Prabhakar #address-cells = <1>; 162a1800417SLad Prabhakar #size-cells = <0>; 163a1800417SLad Prabhakar reg = <0>; 164a1800417SLad Prabhakar 165a1800417SLad Prabhakar cru_parallel_in: endpoint@0 { 166a1800417SLad Prabhakar reg = <0>; 167a1800417SLad Prabhakar remote-endpoint = <&ov5642>; 168a1800417SLad Prabhakar hsync-active = <1>; 169a1800417SLad Prabhakar vsync-active = <1>; 170a1800417SLad Prabhakar }; 171a1800417SLad Prabhakar }; 172a1800417SLad Prabhakar 173a1800417SLad Prabhakar port@1 { 174a1800417SLad Prabhakar #address-cells = <1>; 175a1800417SLad Prabhakar #size-cells = <0>; 176a1800417SLad Prabhakar reg = <1>; 177a1800417SLad Prabhakar 178a1800417SLad Prabhakar cru_csi_in: endpoint@0 { 179a1800417SLad Prabhakar reg = <0>; 180a1800417SLad Prabhakar remote-endpoint = <&csi_cru_in>; 181a1800417SLad Prabhakar }; 182a1800417SLad Prabhakar }; 183a1800417SLad Prabhakar }; 184a1800417SLad Prabhakar }; 185