Lines Matching +full:r9a07g044 +full:- +full:cpg
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
20 - enum:
21 - renesas,r9a07g043u-du # RZ/G2UL
22 - renesas,r9a07g044-du # RZ/G2{L,LC}
23 - renesas,r9a09g057-du # RZ/V2H(P)
24 - items:
25 - enum:
26 - renesas,r9a07g054-du # RZ/V2L
27 - const: renesas,r9a07g044-du # RZ/G2L fallback
37 - description: Main clock
38 - description: Register access clock
39 - description: Video clock
41 clock-names:
43 - const: aclk
44 - const: pclk
45 - const: vclk
50 power-domains:
58 model-dependent. Each port shall have a single endpoint.
61 "^port@[0-1]$":
68 $ref: /schemas/types.yaml#/definitions/phandle-array
71 - description: phandle to VSP instance that serves the DU channel
72 - description: Channel index identifying the LIF instance in that VSP
78 - compatible
79 - reg
80 - interrupts
81 - clocks
82 - clock-names
83 - resets
84 - power-domains
85 - ports
86 - renesas,vsps
91 - if:
95 const: renesas,r9a07g043u-du
104 - port@0
105 - if:
109 const: renesas,r9a07g044-du
120 - port@0
121 - port@1
122 - if:
126 const: renesas,r9a09g057-du
136 - port@0
140 - |
141 #include <dt-bindings/clock/r9a07g044-cpg.h>
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 compatible = "renesas,r9a07g044-du";
148 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
149 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
150 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
151 clock-names = "aclk", "pclk", "vclk";
152 resets = <&cpg R9A07G044_LCDC_RESET_N>;
153 power-domains = <&cpg>;
158 #address-cells = <1>;
159 #size-cells = <0>;
164 remote-endpoint = <&dsi0_in>;