Lines Matching +full:r9a07g044 +full:- +full:cpg

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14   The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15   (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
21       - enum:
22           - renesas,r9a07g043-csi2       # RZ/G2UL
23           - renesas,r9a07g044-csi2       # RZ/G2{L,LC}
24           - renesas,r9a07g054-csi2       # RZ/V2L
25       - const: renesas,rzg2l-csi2
35       - description: Internal clock for connecting CRU and MIPI
36       - description: CRU Main clock
37       - description: CRU Register access clock
39   clock-names:
41       - const: system
42       - const: video
43       - const: apb
45   power-domains:
50       - description: CRU_PRESETN reset terminal
51       - description: CRU_CMN_RSTB reset terminal
53   reset-names:
55       - const: presetn
56       - const: cmn-rstb
63         $ref: /schemas/graph.yaml#/$defs/port-base
66           Input port node, single endpoint describing the CSI-2 transmitter.
70             $ref: video-interfaces.yaml#
74               data-lanes:
81               - clock-lanes
82               - data-lanes
87           Output port node, Image Processing block connected to the CSI-2 receiver.
90       - port@0
91       - port@1
94   - compatible
95   - reg
96   - interrupts
97   - clocks
98   - clock-names
99   - power-domains
100   - resets
101   - reset-names
102   - ports
107   - |
108     #include <dt-bindings/clock/r9a07g044-cpg.h>
109     #include <dt-bindings/interrupt-controller/arm-gic.h>
112         compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
115         clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
116                  <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
117                  <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
118         clock-names = "system", "video", "apb";
119         power-domains = <&cpg>;
120         resets = <&cpg R9A07G044_CRU_PRESETN>,
121                  <&cpg R9A07G044_CRU_CMN_RSTB>;
122         reset-names = "presetn", "cmn-rstb";
125             #address-cells = <1>;
126             #size-cells = <0>;
132                     clock-lanes = <0>;
133                     data-lanes = <1 2>;
134                     remote-endpoint = <&ov5645_ep>;
139                 #address-cells = <1>;
140                 #size-cells = <0>;
146                     remote-endpoint = <&crucsi2>;