Lines Matching +full:r9a07g044 +full:- +full:cpg
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Frame Compression Processor (FCP)
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 R-Car Gen3 and RZ/G2 SoCs. It provides data compression and decompression,
25 - enum:
26 - renesas,fcpv # FCP for VSP
27 - renesas,fcpf # FCP for FDP
28 - items:
29 - enum:
30 - renesas,r9a07g043u-fcpvd # RZ/G2UL
31 - renesas,r9a07g044-fcpvd # RZ/G2{L,LC}
32 - renesas,r9a07g054-fcpvd # RZ/V2L
33 - const: renesas,fcpv # Generic FCP for VSP fallback
40 clock-names: true
45 power-domains:
52 - compatible
53 - reg
54 - clocks
55 - power-domains
56 - resets
61 - if:
66 - renesas,r9a07g043u-fcpvd
67 - renesas,r9a07g044-fcpvd
68 - renesas,r9a07g054-fcpvd
73 - description: Main clock
74 - description: Register access clock
75 - description: Video clock
76 clock-names:
78 - const: aclk
79 - const: pclk
80 - const: vclk
82 - clock-names
87 clock-names: false
90 # R8A7795 (R-Car H3) FCP for VSP-D1
91 - |
92 #include <dt-bindings/clock/renesas-cpg-mssr.h>
93 #include <dt-bindings/power/r8a7795-sysc.h>
98 clocks = <&cpg CPG_MOD 602>;
99 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
100 resets = <&cpg 602>;