/linux/Documentation/devicetree/bindings/clock/ |
H A D | silabs,si5351.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3 16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf 19 - Alvin Šipraga <alsi@bang-olufsen.dk> 24 - silabs,si5351a # Si5351A, 20-QFN package 25 - silabs,si5351a-msop # Si5351A, 10-MSOP package 26 - silabs,si5351b # Si5351B, 20-QFN package 27 - silabs,si5351c # Si5351C, 20-QFN package [all …]
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H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 8 - compatible : shall be one of the following: 9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock 10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock 11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock 12 "apm,xgene-device-clock" - for a X-Gene device clock 13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock 14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock 16 Required properties for SoC or PCP PLL clocks: [all …]
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H A D | qcom,mmcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Multimedia Clock & Reset Controller 10 - Jeffrey Hugo <quic_jhugo@quicinc.com> 11 - Taniya Das <quic_tdas@quicinc.com> 20 - qcom,mmcc-apq8064 21 - qcom,mmcc-apq8084 22 - qcom,mmcc-msm8226 23 - qcom,mmcc-msm8660 [all …]
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H A D | rockchip,rk3328-cru.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip RK3328 Clock and Reset Unit (CRU) 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 15 controllers within the SoC and also implements a reset controller for SoC 19 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be 20 used in device tree sources. Similar macros exist for the reset sources in [all …]
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H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 Clock Control Unit Dividers 11 - Serge Semin <fancer.lancer@gmail.com> 14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 18 IP-blocks or to groups of blocks (clock domains). The transformation is done 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The 21 individually reset by using the domain clocks divider configuration [all …]
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H A D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Reset and Clock Controller 4 The RCC IP is both a reset and a clock controller. 6 Please refer to clock-bindings.txt for common clock controller binding usage. 7 Please also refer to reset.txt for common reset controller binding usage. 10 - compatible: Should be: 11 "st,stm32f42xx-rcc" 12 "st,stm32f469-rcc" 13 "st,stm32f746-rcc" 14 "st,stm32f769-rcc" 16 - reg: should be register base and length as documented in the [all …]
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H A D | rockchip,rk3228-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 --- 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip RK3228 Clock and Reset Unit (CRU) 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 15 controllers within the SoC and also implements a reset controller for SoC 19 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be 20 used in device tree sources. Similar macros exist for the reset sources in [all …]
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/linux/drivers/clk/bcm/ |
H A D | clk-iproc-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include <linux/clk-provider.h> 13 #include "clk-iproc.h" 19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies 20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers 24 /* number of delay loops waiting for PLL to lock */ 75 struct iproc_pll *pll; member 90 return -EINVAL; in pll_calc_param() 92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param() 102 vco_out->ndiv_int = ndiv_int; in pll_calc_param() [all …]
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H A D | clk-iproc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 13 #include <linux/clk-provider.h> 17 #define bit_mask(width) ((1 << (width)) - 1) 22 /* PLL that requires gating through ASIU */ 25 /* PLL that has fractional part of the NDIV */ 29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back 36 * Some PLLs require the PLL SW override bit to be set before changes can be 37 * applied to the PLL 43 * the PLL control register 69 * Some PLLs have an active low reset [all …]
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/linux/drivers/clk/sunxi-ng/ |
H A D | ccu_common.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 9 #include <linux/clk-provider.h> 22 struct ccu_reset reset; member 33 if (common->features & CCU_FEATURE_LOCK_REG) in ccu_helper_wait_for_lock() 34 addr = common->base + common->lock_reg; in ccu_helper_wait_for_lock() 36 addr = common->base + common->reg; in ccu_helper_wait_for_lock() 49 clk_hw_get_rate_range(&common->hw, &min_rate, &max_rate); in ccu_is_better_rate() 57 if (common->features & CCU_FEATURE_CLOSEST_RATE) in ccu_is_better_rate() 58 return abs(current_rate - target_rate) < abs(best_rate - target_rate); in ccu_is_better_rate() [all …]
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/linux/drivers/video/fbdev/via/ |
H A D | via_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 8 * clock and PLL management functions 12 #include <linux/via-core.h> 21 static inline u32 cle266_encode_pll(struct via_pll_config pll) in cle266_encode_pll() argument 23 return (pll.multiplier << 8) in cle266_encode_pll() 24 | (pll.rshift << 6) in cle266_encode_pll() 25 | pll.divisor; in cle266_encode_pll() 28 static inline u32 k800_encode_pll(struct via_pll_config pll) in k800_encode_pll() argument [all …]
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/linux/Documentation/devicetree/bindings/power/reset/ |
H A D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset 3 This node is intended to allow SoC reset in case of software reset 6 The Keystone SoCs can contain up to 4 watchdog timers to reset 7 SoC. Each watchdog timer event input is connected to the Reset Mux 8 block. The Reset Mux block can be configured to cause reset or not. 10 Additionally soft or hard reset can be configured. 14 - compatible: ti,keystone-reset 16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to 17 access pll controller registers and the offset to use 18 reset control registers. [all …]
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/linux/Documentation/devicetree/bindings/usb/ |
H A D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 20 - description: NVIDIA Tegra124 21 const: nvidia,tegra124-xusb 23 - description: NVIDIA Tegra132 25 - const: nvidia,tegra132-xusb [all …]
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H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra210-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 24 - description: base and length of the XUSB IPFS registers [all …]
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/linux/drivers/gpu/drm/msm/hdmi/ |
H A D | hdmi_pll_8960.c | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <linux/clk-provider.h> 24 * HDMI PLL: 26 * To get the parent clock setup properly, we need to plug in hdmi pll 27 * configuration into common-clock-framework. 237 static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data) in pll_write() argument 239 writel(data, pll->mmio + reg); in pll_write() 242 static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg) in pll_read() argument 244 return readl(pll->mmio + reg); in pll_read() 247 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll) in pll_get_phy() argument [all …]
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/linux/drivers/clk/qcom/ |
H A D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/clk-provider.h> 17 #include "clk-pll.h" 26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local 31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable() 39 /* Disable PLL bypass mode. */ in clk_pll_enable() 40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable() 47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable() 51 /* De-assert active-low PLL reset. */ in clk_pll_enable() 52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable() [all …]
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H A D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 9 #include <linux/clk-provider.h> 13 #include "clk-alpha-pll.h" 16 #define PLL_MODE(p) ((p)->offset + 0x0) 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) [all …]
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/linux/arch/mips/boot/dts/qca/ |
H A D | ar9132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ath79-clk.h> 7 #address-cells = <1>; 8 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 17 clocks = <&pll ATH79_CLK_CPU>; 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 25 interrupt-controller; [all …]
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H A D | ar9331.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ath79-clk.h> 7 #address-cells = <1>; 8 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 17 clocks = <&pll ATH79_CLK_CPU>; 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar7100-cpu-intc"; 25 interrupt-controller; [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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/linux/drivers/clk/tegra/ |
H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 9 #include <linux/clk-provider.h> 73 * struct tegra_clk_sync_source - external clock source from codec 75 * @hw: handle between common and hardware-specific interfaces 95 * struct tegra_clk_frac_div - fractional divider clock 97 * @hw: handle between common and hardware-specific interfaces 99 * @flags: hardware-specific flags 106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 108 * flag indicates that this divider is for fixed rate PLL. [all …]
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/linux/arch/arm/mach-davinci/ |
H A D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only 49 /* Switch CPU PLL to bypass mode */ in davinci_pm_suspend() 56 /* Powerdown CPU PLL */ in davinci_pm_suspend() 73 /* put CPU PLL in reset */ in davinci_pm_suspend() 78 /* put CPU PLL in power down */ in davinci_pm_suspend() 83 /* wait for CPU PLL reset */ in davinci_pm_suspend() 86 /* bring CPU PLL out of reset */ in davinci_pm_suspend() 91 /* Wait for CPU PLL to lock */ in davinci_pm_suspend() 94 /* Remove CPU PLL from bypass mode */ in davinci_pm_suspend() 111 ret = -EINVAL; in davinci_pm_enter() [all …]
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/linux/drivers/clk/meson/ |
H A D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0 11 * In the most basic form, a Meson PLL is composed as follows: 13 * PLL 14 * +--------------------------------+ 16 * | +--+ | 17 * in >>-----[ /N ]--->| | +-----+ | 18 * | | |------| DCO |---->> out 19 * | +--------->| | +--v--+ | 20 * | | +--+ | | 22 * | +--[ *(M + (F/Fmax) ]<--+ | [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | adi,adau1701.txt | 5 - compatible: Should contain "adi,adau1701" 6 - reg: The i2c address. Value depends on the state of ADDR0 11 - reset-gpio: A GPIO spec to define which pin is connected to the 12 chip's !RESET pin. If specified, the driver will 13 assert a hardware reset at probe time. 14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs 15 the ADAU's PLL config pins are connected to. 19 - adi,pin-config: An array of 12 numerical values selecting one of the 23 - avdd-supply: Power supply for AVDD, providing 3.3V 24 - dvdd-supply: Power supply for DVDD, providing 3.3V [all …]
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