Lines Matching +full:pll +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
61 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
62 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
63 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
306 /* TRION PLL specific settings and offsets */
310 /* LUCID PLL specific settings and offsets */
313 /* LUCID 5LPE PLL specific settings and offsets */
319 /* LUCID EVO PLL specific settings and offsets */
326 /* ZONDA PLL specific */
332 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
335 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
343 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
349 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
351 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
355 for (count = 200; count > 0; count--) { in wait_for_pll()
356 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
368 return -ETIMEDOUT; in wait_for_pll()
371 #define wait_for_pll_enable_active(pll) \ argument
372 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
374 #define wait_for_pll_enable_lock(pll) \ argument
375 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
377 #define wait_for_zonda_pll_freq_lock(pll) \ argument
378 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
380 #define wait_for_pll_disable(pll) \ argument
381 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
383 #define wait_for_pll_offline(pll) \ argument
384 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
386 #define wait_for_pll_update(pll) \ argument
387 wait_for_pll(pll, PLL_UPDATE, 1, "update")
389 #define wait_for_pll_update_ack_set(pll) \ argument
390 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
392 #define wait_for_pll_update_ack_clear(pll) \ argument
393 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
402 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
407 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
408 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
409 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
411 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
412 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
413 config->config_ctl_hi_val); in clk_alpha_pll_configure()
415 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
416 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
418 val = config->main_output_mask; in clk_alpha_pll_configure()
419 val |= config->aux_output_mask; in clk_alpha_pll_configure()
420 val |= config->aux2_output_mask; in clk_alpha_pll_configure()
421 val |= config->early_output_mask; in clk_alpha_pll_configure()
422 val |= config->pre_div_val; in clk_alpha_pll_configure()
423 val |= config->post_div_val; in clk_alpha_pll_configure()
424 val |= config->vco_val; in clk_alpha_pll_configure()
425 val |= config->alpha_en_mask; in clk_alpha_pll_configure()
426 val |= config->alpha_mode_mask; in clk_alpha_pll_configure()
428 mask = config->main_output_mask; in clk_alpha_pll_configure()
429 mask |= config->aux_output_mask; in clk_alpha_pll_configure()
430 mask |= config->aux2_output_mask; in clk_alpha_pll_configure()
431 mask |= config->early_output_mask; in clk_alpha_pll_configure()
432 mask |= config->pre_div_mask; in clk_alpha_pll_configure()
433 mask |= config->post_div_mask; in clk_alpha_pll_configure()
434 mask |= config->vco_mask; in clk_alpha_pll_configure()
436 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
438 if (config->test_ctl_mask) in clk_alpha_pll_configure()
439 regmap_update_bits(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
440 config->test_ctl_mask, in clk_alpha_pll_configure()
441 config->test_ctl_val); in clk_alpha_pll_configure()
443 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
444 config->test_ctl_val); in clk_alpha_pll_configure()
446 if (config->test_ctl_hi_mask) in clk_alpha_pll_configure()
447 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
448 config->test_ctl_hi_mask, in clk_alpha_pll_configure()
449 config->test_ctl_hi_val); in clk_alpha_pll_configure()
451 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
452 config->test_ctl_hi_val); in clk_alpha_pll_configure()
454 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
455 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
462 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
465 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
471 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
474 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
481 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
487 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
490 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
494 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
495 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
500 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
506 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
511 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
517 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
520 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
540 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
544 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
553 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
560 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
567 * de-asserting the reset. in clk_alpha_pll_enable()
572 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
577 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
581 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
592 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
595 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
606 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
613 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
651 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
653 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
654 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
657 if (rate >= v->min_freq && rate <= v->max_freq) in alpha_pll_find_vco()
668 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
669 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
671 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
673 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
675 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
677 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
681 a = low & GENMASK(alpha_width - 1, 0); in clk_alpha_pll_recalc_rate()
685 a >>= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_recalc_rate()
692 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
697 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
699 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
700 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
707 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
708 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
709 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
711 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
714 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
718 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
720 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
725 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
729 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
735 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
738 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
739 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
742 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
749 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
751 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
755 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
756 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
757 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
759 return -EINVAL; in __clk_alpha_pll_set_rate()
762 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
765 a <<= alpha_width - ALPHA_BITWIDTH; in __clk_alpha_pll_set_rate()
768 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
770 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
773 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
775 vco->val << PLL_VCO_SHIFT); in __clk_alpha_pll_set_rate()
778 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
781 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
801 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
802 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
807 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
810 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
811 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
816 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_huayra_2290_pll_configure() argument
821 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_huayra_2290_pll_configure()
822 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_huayra_2290_pll_configure()
823 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_huayra_2290_pll_configure()
824 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_huayra_2290_pll_configure()
825 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_huayra_2290_pll_configure()
826 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_huayra_2290_pll_configure()
827 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_huayra_2290_pll_configure()
828 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_huayra_2290_pll_configure()
829 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_huayra_2290_pll_configure()
832 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_huayra_2290_pll_configure()
833 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
835 /* Wait 5 us between setting BYPASS and deasserting reset */ in clk_huayra_2290_pll_configure()
838 /* Take PLL out from reset state */ in clk_huayra_2290_pll_configure()
839 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_huayra_2290_pll_configure()
840 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
845 /* Enable PLL output */ in clk_huayra_2290_pll_configure()
846 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_huayra_2290_pll_configure()
855 * of [-0.5, 0.5). in alpha_huayra_pll_calc_rate()
857 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_calc_rate()
858 l -= 1; in alpha_huayra_pll_calc_rate()
887 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value in alpha_huayra_pll_round_rate()
890 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_round_rate()
901 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
904 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
905 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
908 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
916 * M is a signed number (-128 to 127) and N is unsigned in alpha_pll_huayra_recalc_rate()
917 * (0 to 255). M/N has to be within +/-0.5. in alpha_pll_huayra_recalc_rate()
920 * range [-0.5, 0.5). in alpha_pll_huayra_recalc_rate()
934 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { in alpha_pll_huayra_recalc_rate()
935 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; in alpha_pll_huayra_recalc_rate()
938 rate -= tmp; in alpha_pll_huayra_recalc_rate()
954 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
959 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
962 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
965 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
972 return -EBUSY; in alpha_pll_huayra_set_rate()
975 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
978 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
981 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
982 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
985 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
988 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
1002 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
1008 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
1009 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
1018 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
1020 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
1025 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
1026 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
1030 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
1039 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
1043 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
1045 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
1049 /* Enable the PLL outputs */ in clk_trion_pll_enable()
1050 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
1055 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
1056 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
1062 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
1063 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
1067 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
1077 /* Disable the global PLL output */ in clk_trion_pll_disable()
1078 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1082 /* Disable the PLL outputs */ in clk_trion_pll_disable()
1083 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
1088 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
1089 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
1090 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1096 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
1097 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
1099 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
1100 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
1155 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1158 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
1161 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1186 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
1189 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
1195 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1202 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1205 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1208 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1220 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1223 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ in clk_alpha_pll_postdiv_set_rate()
1224 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; in clk_alpha_pll_postdiv_set_rate()
1226 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1227 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1244 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1249 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1250 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1251 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1252 config->config_ctl_val); in clk_fabia_pll_configure()
1253 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1254 config->config_ctl_hi_val); in clk_fabia_pll_configure()
1255 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1256 config->user_ctl_val); in clk_fabia_pll_configure()
1257 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1258 config->user_ctl_hi_val); in clk_fabia_pll_configure()
1259 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1260 config->test_ctl_val); in clk_fabia_pll_configure()
1261 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1262 config->test_ctl_hi_val); in clk_fabia_pll_configure()
1264 if (config->post_div_mask) { in clk_fabia_pll_configure()
1265 mask = config->post_div_mask; in clk_fabia_pll_configure()
1266 val = config->post_div_val; in clk_fabia_pll_configure()
1267 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1270 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1271 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1274 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1277 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1284 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1286 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1288 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1297 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1300 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1304 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1308 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1312 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1316 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1321 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1325 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1329 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1334 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1341 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1343 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1345 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1355 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1360 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1364 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1365 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1371 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1372 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1374 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1375 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1392 return -EINVAL; in alpha_pll_check_rate_margin()
1401 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1402 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1413 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1414 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1416 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1421 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1425 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1430 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1431 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1439 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1441 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1442 return -EINVAL; in alpha_pll_fabia_prepare()
1445 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1446 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1450 return -EINVAL; in alpha_pll_fabia_prepare()
1459 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1460 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1462 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1465 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1497 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1501 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1505 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1506 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1508 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1509 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1510 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1521 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1522 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1525 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1527 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1528 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1530 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1531 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1532 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1544 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1546 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1547 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1554 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1555 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1559 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1560 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1561 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1566 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1567 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, in clk_trion_pll_postdiv_set_rate()
1568 val << pll->post_div_shift); in clk_trion_pll_postdiv_set_rate()
1581 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1583 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1584 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1590 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1594 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1595 * no-operation. in clk_alpha_pll_postdiv_fabia_set_rate()
1597 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1605 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1606 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1607 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1612 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1613 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1614 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1625 * clk_trion_pll_configure - configure the trion pll
1627 * @pll: clk alpha pll
1629 * @config: configuration to apply for pll
1631 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1635 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1636 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1638 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1639 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1643 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1644 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1645 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1646 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1647 config->config_ctl_val); in clk_trion_pll_configure()
1648 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1649 config->config_ctl_hi_val); in clk_trion_pll_configure()
1650 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1651 config->config_ctl_hi1_val); in clk_trion_pll_configure()
1652 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1653 config->user_ctl_val); in clk_trion_pll_configure()
1654 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1655 config->user_ctl_hi_val); in clk_trion_pll_configure()
1656 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1657 config->user_ctl_hi1_val); in clk_trion_pll_configure()
1658 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1659 config->test_ctl_val); in clk_trion_pll_configure()
1660 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1661 config->test_ctl_hi_val); in clk_trion_pll_configure()
1662 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1663 config->test_ctl_hi1_val); in clk_trion_pll_configure()
1665 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1668 /* Disable PLL output */ in clk_trion_pll_configure()
1669 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1672 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1674 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1675 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1680 * The TRION PLL requires a power-on self-calibration which happens when the
1681 * PLL comes out of reset. Calibrate in case it is not completed.
1685 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1690 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1715 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1717 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1727 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); in __alpha_pll_trion_set_rate()
1728 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1730 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1731 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1737 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1739 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1740 return -EINVAL; in __alpha_pll_trion_set_rate()
1744 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1749 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1754 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1794 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1797 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1798 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1799 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1800 config->user_ctl_val); in clk_agera_pll_configure()
1801 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1802 config->config_ctl_val); in clk_agera_pll_configure()
1803 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1804 config->config_ctl_hi_val); in clk_agera_pll_configure()
1805 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1806 config->test_ctl_val); in clk_agera_pll_configure()
1807 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1808 config->test_ctl_hi_val); in clk_agera_pll_configure()
1815 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1816 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1827 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1828 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1831 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1847 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1849 * @pll: clk alpha pll
1851 * @config: configuration to apply for pll
1853 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_5lpe_pll_configure() argument
1857 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_5lpe_pll_configure()
1858 * RCGs that will lock up if we disable the PLL below. in clk_lucid_5lpe_pll_configure()
1860 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_5lpe_pll_configure()
1861 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); in clk_lucid_5lpe_pll_configure()
1865 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_lucid_5lpe_pll_configure()
1866 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_lucid_5lpe_pll_configure()
1867 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_5lpe_pll_configure()
1868 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_lucid_5lpe_pll_configure()
1869 config->config_ctl_val); in clk_lucid_5lpe_pll_configure()
1870 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1871 config->config_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1872 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1873 config->config_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1874 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_lucid_5lpe_pll_configure()
1875 config->user_ctl_val); in clk_lucid_5lpe_pll_configure()
1876 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1877 config->user_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1878 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1879 config->user_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1880 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_lucid_5lpe_pll_configure()
1881 config->test_ctl_val); in clk_lucid_5lpe_pll_configure()
1882 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1883 config->test_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1884 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1885 config->test_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1887 /* Disable PLL output */ in clk_lucid_5lpe_pll_configure()
1888 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_5lpe_pll_configure()
1891 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_5lpe_pll_configure()
1893 /* Place the PLL in STANDBY mode */ in clk_lucid_5lpe_pll_configure()
1894 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_5lpe_pll_configure()
1900 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1904 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1913 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1916 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1917 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) in alpha_pll_lucid_5lpe_enable()
1920 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1924 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1926 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1930 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1931 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1935 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1936 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1941 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
1945 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
1955 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
1956 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
1960 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
1961 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
1965 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
1966 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
1970 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1971 * when the PLL comes out of reset. Calibrate in case it is not completed.
1975 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
1981 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
1987 return -EINVAL; in alpha_pll_lucid_5lpe_prepare()
2010 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
2011 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
2016 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
2017 * no-operation. in __clk_lucid_pll_postdiv_set_rate()
2019 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
2026 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
2027 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
2028 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
2029 return -EINVAL; in __clk_lucid_pll_postdiv_set_rate()
2033 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
2034 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
2035 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
2040 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2041 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
2042 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2078 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
2081 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
2082 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
2083 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
2084 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
2085 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
2086 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
2087 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
2088 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
2089 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
2090 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
2091 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
2093 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
2095 /* Disable PLL output */ in clk_zonda_pll_configure()
2096 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
2099 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
2101 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
2102 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
2108 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
2109 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
2113 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
2120 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
2123 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
2124 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
2128 * de-asserting the reset. in clk_zonda_pll_enable()
2132 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
2135 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
2137 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
2141 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
2143 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
2147 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
2148 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
2150 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
2151 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
2158 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
2159 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
2162 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
2170 /* Disable the global PLL output */ in clk_zonda_pll_disable()
2171 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
2173 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
2174 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
2176 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
2177 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2179 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
2180 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
2196 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
2199 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2212 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2213 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2222 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2226 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2228 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2232 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2247 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2250 u32 lval = config->l; in clk_lucid_evo_pll_configure()
2253 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_evo_pll_configure()
2254 * RCGs that will lock up if we disable the PLL below. in clk_lucid_evo_pll_configure()
2256 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_evo_pll_configure()
2257 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); in clk_lucid_evo_pll_configure()
2262 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2263 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2264 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2265 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2266 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2267 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2268 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2269 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2270 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2271 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2272 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_evo_pll_configure()
2274 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2275 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2277 /* Set operation mode to STANDBY and de-assert the reset */ in clk_lucid_evo_pll_configure()
2278 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2279 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2283 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_ole_pll_configure() argument
2286 u32 lval = config->l; in clk_lucid_ole_pll_configure()
2290 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_ole_pll_configure()
2291 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_ole_pll_configure()
2292 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_ole_pll_configure()
2293 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_ole_pll_configure()
2294 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2295 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_ole_pll_configure()
2296 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_ole_pll_configure()
2297 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_ole_pll_configure()
2298 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_ole_pll_configure()
2299 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2300 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_ole_pll_configure()
2302 /* Disable PLL output */ in clk_lucid_ole_pll_configure()
2303 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_ole_pll_configure()
2305 /* Set operation mode to STANDBY and de-assert the reset */ in clk_lucid_ole_pll_configure()
2306 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_ole_pll_configure()
2307 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_ole_pll_configure()
2313 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2314 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2318 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2327 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2330 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2331 if (trion_pll_is_enabled(pll, regmap)) in alpha_pll_lucid_evo_enable()
2334 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2339 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2341 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2345 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2346 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2350 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2351 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2360 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) in _alpha_pll_lucid_evo_disable() argument
2362 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2363 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2367 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2377 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2378 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2382 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2383 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2387 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2388 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2390 if (reset) in _alpha_pll_lucid_evo_disable()
2391 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2394 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) in _alpha_pll_lucid_evo_prepare() argument
2396 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2402 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2408 return -EINVAL; in _alpha_pll_lucid_evo_prepare()
2414 _alpha_pll_lucid_evo_disable(hw, reset); in _alpha_pll_lucid_evo_prepare()
2442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2443 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2446 regmap_read(regmap, PLL_L_VAL(pll), &l); in alpha_pll_lucid_evo_recalc_rate()
2448 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); in alpha_pll_lucid_evo_recalc_rate()
2450 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2497 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2500 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2501 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2502 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2503 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2504 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2505 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2506 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2507 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2509 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2511 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2520 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2523 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_rivian_evo_pll_recalc_rate()
2531 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_round_rate() local
2537 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_rivian_evo_pll_round_rate()
2540 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_round_rate()
2541 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_round_rate()
2555 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_stromer_pll_configure() argument
2560 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_stromer_pll_configure()
2561 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_stromer_pll_configure()
2562 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_stromer_pll_configure()
2564 if (pll_has_64bit_config(pll)) in clk_stromer_pll_configure()
2565 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_stromer_pll_configure()
2566 config->config_ctl_hi_val); in clk_stromer_pll_configure()
2568 if (pll_alpha_width(pll) > 32) in clk_stromer_pll_configure()
2569 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_stromer_pll_configure()
2571 val = config->main_output_mask; in clk_stromer_pll_configure()
2572 val |= config->aux_output_mask; in clk_stromer_pll_configure()
2573 val |= config->aux2_output_mask; in clk_stromer_pll_configure()
2574 val |= config->early_output_mask; in clk_stromer_pll_configure()
2575 val |= config->pre_div_val; in clk_stromer_pll_configure()
2576 val |= config->post_div_val; in clk_stromer_pll_configure()
2577 val |= config->vco_val; in clk_stromer_pll_configure()
2578 val |= config->alpha_en_mask; in clk_stromer_pll_configure()
2579 val |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2581 mask = config->main_output_mask; in clk_stromer_pll_configure()
2582 mask |= config->aux_output_mask; in clk_stromer_pll_configure()
2583 mask |= config->aux2_output_mask; in clk_stromer_pll_configure()
2584 mask |= config->early_output_mask; in clk_stromer_pll_configure()
2585 mask |= config->pre_div_mask; in clk_stromer_pll_configure()
2586 mask |= config->post_div_mask; in clk_stromer_pll_configure()
2587 mask |= config->vco_mask; in clk_stromer_pll_configure()
2588 mask |= config->alpha_en_mask; in clk_stromer_pll_configure()
2589 mask |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2591 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_stromer_pll_configure()
2593 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ in clk_stromer_pll_configure()
2594 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; in clk_stromer_pll_configure()
2595 val_u |= config->lock_det; in clk_stromer_pll_configure()
2597 mask_u = config->status_mask; in clk_stromer_pll_configure()
2598 mask_u |= config->lock_det; in clk_stromer_pll_configure()
2600 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); in clk_stromer_pll_configure()
2601 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_stromer_pll_configure()
2602 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_stromer_pll_configure()
2604 if (pll->flags & SUPPORTS_FSM_MODE) in clk_stromer_pll_configure()
2605 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_stromer_pll_configure()
2615 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, in clk_alpha_pll_stromer_determine_rate()
2624 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_set_rate() local
2631 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_set_rate()
2633 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; in clk_alpha_pll_stromer_set_rate()
2634 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_set_rate()
2635 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_set_rate()
2638 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_set_rate()
2645 * Stromer PLL supports Dynamic programming. in clk_alpha_pll_stromer_set_rate()
2646 * It allows the PLL frequency to be changed on-the-fly without first in clk_alpha_pll_stromer_set_rate()
2649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in clk_alpha_pll_stromer_set_rate()
2652 ret = wait_for_pll_update(pll); in clk_alpha_pll_stromer_set_rate()
2656 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_set_rate()
2673 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_plus_set_rate() local
2674 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_stromer_plus_set_rate()
2680 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); in clk_alpha_pll_stromer_plus_set_rate()
2684 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); in clk_alpha_pll_stromer_plus_set_rate()
2689 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_plus_set_rate()
2692 a <<= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_stromer_plus_set_rate()
2694 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_plus_set_rate()
2695 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_plus_set_rate()
2698 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_plus_set_rate()
2701 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); in clk_alpha_pll_stromer_plus_set_rate()
2705 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, in clk_alpha_pll_stromer_plus_set_rate()
2711 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_plus_set_rate()
2713 pr_err("Wait for PLL enable lock failed [%s] %d\n", in clk_alpha_pll_stromer_plus_set_rate()
2719 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, in clk_alpha_pll_stromer_plus_set_rate()
2735 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_regera_pll_configure() argument
2738 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_regera_pll_configure()
2739 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_regera_pll_configure()
2740 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_regera_pll_configure()
2741 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_regera_pll_configure()
2742 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_regera_pll_configure()
2743 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_regera_pll_configure()
2744 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_regera_pll_configure()
2745 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_regera_pll_configure()
2746 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_regera_pll_configure()
2747 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_regera_pll_configure()
2748 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_regera_pll_configure()
2751 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_regera_pll_configure()