1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8  * clock and PLL management functions
12 #include <linux/via-core.h>
21 static inline u32 cle266_encode_pll(struct via_pll_config pll)  in cle266_encode_pll()  argument
23 	return (pll.multiplier << 8)  in cle266_encode_pll()
24 		| (pll.rshift << 6)  in cle266_encode_pll()
25 		| pll.divisor;  in cle266_encode_pll()
28 static inline u32 k800_encode_pll(struct via_pll_config pll)  in k800_encode_pll()  argument
30 	return ((pll.divisor - 2) << 16)  in k800_encode_pll()
31 		| (pll.rshift << 10)  in k800_encode_pll()
32 		| (pll.multiplier - 2);  in k800_encode_pll()
35 static inline u32 vx855_encode_pll(struct via_pll_config pll)  in vx855_encode_pll()  argument
37 	return (pll.divisor << 16)  in vx855_encode_pll()
38 		| (pll.rshift << 10)  in vx855_encode_pll()
39 		| pll.multiplier;  in vx855_encode_pll()
44 	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */  in cle266_set_primary_pll_encoded()
47 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */  in cle266_set_primary_pll_encoded()
52 	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */  in k800_set_primary_pll_encoded()
56 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */  in k800_set_primary_pll_encoded()
61 	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */  in cle266_set_secondary_pll_encoded()
64 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */  in cle266_set_secondary_pll_encoded()
69 	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */  in k800_set_secondary_pll_encoded()
73 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */  in k800_set_secondary_pll_encoded()
78 	via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */  in set_engine_pll_encoded()
82 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */  in set_engine_pll_encoded()
270 	printk(KERN_INFO "Using undocumented set PLL state.\n%s", via_slap);  in dummy_set_pll_state()
275 	printk(KERN_INFO "Using undocumented set PLL.\n%s", via_slap);  in dummy_set_pll()
287 		clock->set_primary_clock_state = dummy_set_clock_state;  in via_clock_init()
288 		clock->set_primary_clock_source = dummy_set_clock_source;  in via_clock_init()
289 		clock->set_primary_pll_state = dummy_set_pll_state;  in via_clock_init()
290 		clock->set_primary_pll = cle266_set_primary_pll;  in via_clock_init()
292 		clock->set_secondary_clock_state = dummy_set_clock_state;  in via_clock_init()
293 		clock->set_secondary_clock_source = dummy_set_clock_source;  in via_clock_init()
294 		clock->set_secondary_pll_state = dummy_set_pll_state;  in via_clock_init()
295 		clock->set_secondary_pll = cle266_set_secondary_pll;  in via_clock_init()
297 		clock->set_engine_pll_state = dummy_set_pll_state;  in via_clock_init()
298 		clock->set_engine_pll = dummy_set_pll;  in via_clock_init()
309 		clock->set_primary_clock_state = set_primary_clock_state;  in via_clock_init()
310 		clock->set_primary_clock_source = set_primary_clock_source;  in via_clock_init()
311 		clock->set_primary_pll_state = set_primary_pll_state;  in via_clock_init()
312 		clock->set_primary_pll = k800_set_primary_pll;  in via_clock_init()
314 		clock->set_secondary_clock_state = set_secondary_clock_state;  in via_clock_init()
315 		clock->set_secondary_clock_source = set_secondary_clock_source;  in via_clock_init()
316 		clock->set_secondary_pll_state = set_secondary_pll_state;  in via_clock_init()
317 		clock->set_secondary_pll = k800_set_secondary_pll;  in via_clock_init()
319 		clock->set_engine_pll_state = set_engine_pll_state;  in via_clock_init()
320 		clock->set_engine_pll = k800_set_engine_pll;  in via_clock_init()
324 		clock->set_primary_clock_state = set_primary_clock_state;  in via_clock_init()
325 		clock->set_primary_clock_source = set_primary_clock_source;  in via_clock_init()
326 		clock->set_primary_pll_state = set_primary_pll_state;  in via_clock_init()
327 		clock->set_primary_pll = vx855_set_primary_pll;  in via_clock_init()
329 		clock->set_secondary_clock_state = set_secondary_clock_state;  in via_clock_init()
330 		clock->set_secondary_clock_source = set_secondary_clock_source;  in via_clock_init()
331 		clock->set_secondary_pll_state = set_secondary_pll_state;  in via_clock_init()
332 		clock->set_secondary_pll = vx855_set_secondary_pll;  in via_clock_init()
334 		clock->set_engine_pll_state = set_engine_pll_state;  in via_clock_init()
335 		clock->set_engine_pll = vx855_set_engine_pll;  in via_clock_init()
341 		/* The OLPC XO-1.5 cannot suspend/resume reliably if the  in via_clock_init()
346 		 * The only known stable scenario is to leave this bits as-is,  in via_clock_init()
350 		clock->set_primary_clock_state = noop_set_clock_state;  in via_clock_init()
351 		clock->set_secondary_clock_state = noop_set_clock_state;  in via_clock_init()