122f65a38SJerome Brunet // SPDX-License-Identifier: GPL-2.0
27a29a869SCarlo Caione /*
37a29a869SCarlo Caione * Copyright (c) 2015 Endless Mobile, Inc.
47a29a869SCarlo Caione * Author: Carlo Caione <carlo@endlessm.com>
57a29a869SCarlo Caione *
68289aafaSJerome Brunet * Copyright (c) 2018 Baylibre, SAS.
78289aafaSJerome Brunet * Author: Jerome Brunet <jbrunet@baylibre.com>
87a29a869SCarlo Caione */
97a29a869SCarlo Caione
107a29a869SCarlo Caione /*
117a29a869SCarlo Caione * In the most basic form, a Meson PLL is composed as follows:
127a29a869SCarlo Caione *
137a29a869SCarlo Caione * PLL
1487173557SJerome Brunet * +--------------------------------+
157a29a869SCarlo Caione * | |
1687173557SJerome Brunet * | +--+ |
1787173557SJerome Brunet * in >>-----[ /N ]--->| | +-----+ |
1887173557SJerome Brunet * | | |------| DCO |---->> out
1987173557SJerome Brunet * | +--------->| | +--v--+ |
2087173557SJerome Brunet * | | +--+ | |
2187173557SJerome Brunet * | | | |
2287173557SJerome Brunet * | +--[ *(M + (F/Fmax) ]<--+ |
237a29a869SCarlo Caione * | |
2487173557SJerome Brunet * +--------------------------------+
257a29a869SCarlo Caione *
2687173557SJerome Brunet * out = in * (m + frac / frac_max) / n
277a29a869SCarlo Caione */
287a29a869SCarlo Caione
297a29a869SCarlo Caione #include <linux/clk-provider.h>
307a29a869SCarlo Caione #include <linux/delay.h>
317a29a869SCarlo Caione #include <linux/err.h>
327a29a869SCarlo Caione #include <linux/io.h>
3394aa8a41SJerome Brunet #include <linux/math64.h>
347a29a869SCarlo Caione #include <linux/module.h>
357a29a869SCarlo Caione
36889c2b7eSJerome Brunet #include "clk-regmap.h"
37889c2b7eSJerome Brunet #include "clk-pll.h"
387a29a869SCarlo Caione
39722825dcSJerome Brunet static inline struct meson_clk_pll_data *
meson_clk_pll_data(struct clk_regmap * clk)40722825dcSJerome Brunet meson_clk_pll_data(struct clk_regmap *clk)
41722825dcSJerome Brunet {
42722825dcSJerome Brunet return (struct meson_clk_pll_data *)clk->data;
43722825dcSJerome Brunet }
447a29a869SCarlo Caione
__pll_round_closest_mult(struct meson_clk_pll_data * pll)458eed1db1SJerome Brunet static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)
468eed1db1SJerome Brunet {
478eed1db1SJerome Brunet if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&
488eed1db1SJerome Brunet !MESON_PARM_APPLICABLE(&pll->frac))
498eed1db1SJerome Brunet return 1;
508eed1db1SJerome Brunet
518eed1db1SJerome Brunet return 0;
528eed1db1SJerome Brunet }
538eed1db1SJerome Brunet
__pll_params_to_rate(unsigned long parent_rate,unsigned int m,unsigned int n,unsigned int frac,struct meson_clk_pll_data * pll)548289aafaSJerome Brunet static unsigned long __pll_params_to_rate(unsigned long parent_rate,
558eed1db1SJerome Brunet unsigned int m, unsigned int n,
568eed1db1SJerome Brunet unsigned int frac,
578289aafaSJerome Brunet struct meson_clk_pll_data *pll)
588289aafaSJerome Brunet {
598eed1db1SJerome Brunet u64 rate = (u64)parent_rate * m;
608289aafaSJerome Brunet
618289aafaSJerome Brunet if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
628289aafaSJerome Brunet u64 frac_rate = (u64)parent_rate * frac;
638289aafaSJerome Brunet
648289aafaSJerome Brunet rate += DIV_ROUND_UP_ULL(frac_rate,
658289aafaSJerome Brunet (1 << pll->frac.width));
668289aafaSJerome Brunet }
678289aafaSJerome Brunet
688eed1db1SJerome Brunet return DIV_ROUND_UP_ULL(rate, n);
698289aafaSJerome Brunet }
708289aafaSJerome Brunet
meson_clk_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)717a29a869SCarlo Caione static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
727a29a869SCarlo Caione unsigned long parent_rate)
737a29a869SCarlo Caione {
74722825dcSJerome Brunet struct clk_regmap *clk = to_clk_regmap(hw);
75722825dcSJerome Brunet struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
768eed1db1SJerome Brunet unsigned int m, n, frac;
777a29a869SCarlo Caione
788eed1db1SJerome Brunet n = meson_parm_read(clk->map, &pll->n);
79d8488a41SRemi Pommarel
80d8488a41SRemi Pommarel /*
81d8488a41SRemi Pommarel * On some HW, N is set to zero on init. This value is invalid as
82d8488a41SRemi Pommarel * it would result in a division by zero. The rate can't be
83d8488a41SRemi Pommarel * calculated in this case
84d8488a41SRemi Pommarel */
85d8488a41SRemi Pommarel if (n == 0)
86d8488a41SRemi Pommarel return 0;
87d8488a41SRemi Pommarel
888eed1db1SJerome Brunet m = meson_parm_read(clk->map, &pll->m);
897d3142e5SJerome Brunet
908289aafaSJerome Brunet frac = MESON_PARM_APPLICABLE(&pll->frac) ?
918289aafaSJerome Brunet meson_parm_read(clk->map, &pll->frac) :
928289aafaSJerome Brunet 0;
9394aa8a41SJerome Brunet
948eed1db1SJerome Brunet return __pll_params_to_rate(parent_rate, m, n, frac, pll);
9594aa8a41SJerome Brunet }
9694aa8a41SJerome Brunet
__pll_params_with_frac(unsigned long rate,unsigned long parent_rate,unsigned int m,unsigned int n,struct meson_clk_pll_data * pll)978eed1db1SJerome Brunet static unsigned int __pll_params_with_frac(unsigned long rate,
988289aafaSJerome Brunet unsigned long parent_rate,
998eed1db1SJerome Brunet unsigned int m,
1008eed1db1SJerome Brunet unsigned int n,
1018289aafaSJerome Brunet struct meson_clk_pll_data *pll)
1028289aafaSJerome Brunet {
1038eed1db1SJerome Brunet unsigned int frac_max = (1 << pll->frac.width);
1048eed1db1SJerome Brunet u64 val = (u64)rate * n;
1058eed1db1SJerome Brunet
1068eed1db1SJerome Brunet /* Bail out if we are already over the requested rate */
1078eed1db1SJerome Brunet if (rate < parent_rate * m / n)
1088eed1db1SJerome Brunet return 0;
1098289aafaSJerome Brunet
1100a1be867SJerome Brunet if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
1110a1be867SJerome Brunet val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
1120a1be867SJerome Brunet else
1138289aafaSJerome Brunet val = div_u64(val * frac_max, parent_rate);
1140a1be867SJerome Brunet
1158eed1db1SJerome Brunet val -= m * frac_max;
1168289aafaSJerome Brunet
1178eed1db1SJerome Brunet return min((unsigned int)val, (frac_max - 1));
1188289aafaSJerome Brunet }
1198289aafaSJerome Brunet
meson_clk_pll_is_better(unsigned long rate,unsigned long best,unsigned long now,struct meson_clk_pll_data * pll)120dd601dbcSJerome Brunet static bool meson_clk_pll_is_better(unsigned long rate,
121dd601dbcSJerome Brunet unsigned long best,
122dd601dbcSJerome Brunet unsigned long now,
1238289aafaSJerome Brunet struct meson_clk_pll_data *pll)
1248289aafaSJerome Brunet {
1258eed1db1SJerome Brunet if (__pll_round_closest_mult(pll)) {
126dd601dbcSJerome Brunet /* Round Closest */
127dd601dbcSJerome Brunet if (abs(now - rate) < abs(best - rate))
128dd601dbcSJerome Brunet return true;
1298eed1db1SJerome Brunet } else {
1308eed1db1SJerome Brunet /* Round down */
131d6f987c8SMartin Blumenstingl if (now <= rate && best < now)
1328eed1db1SJerome Brunet return true;
133dd601dbcSJerome Brunet }
134dd601dbcSJerome Brunet
135dd601dbcSJerome Brunet return false;
136dd601dbcSJerome Brunet }
137dd601dbcSJerome Brunet
meson_clk_get_pll_table_index(unsigned int index,unsigned int * m,unsigned int * n,struct meson_clk_pll_data * pll)1388eed1db1SJerome Brunet static int meson_clk_get_pll_table_index(unsigned int index,
1398eed1db1SJerome Brunet unsigned int *m,
1408eed1db1SJerome Brunet unsigned int *n,
141dd601dbcSJerome Brunet struct meson_clk_pll_data *pll)
142dd601dbcSJerome Brunet {
1438eed1db1SJerome Brunet if (!pll->table[index].n)
1448eed1db1SJerome Brunet return -EINVAL;
1458eed1db1SJerome Brunet
1468eed1db1SJerome Brunet *m = pll->table[index].m;
1478eed1db1SJerome Brunet *n = pll->table[index].n;
1488eed1db1SJerome Brunet
1498eed1db1SJerome Brunet return 0;
1508eed1db1SJerome Brunet }
1518eed1db1SJerome Brunet
meson_clk_get_pll_range_m(unsigned long rate,unsigned long parent_rate,unsigned int n,struct meson_clk_pll_data * pll)1528eed1db1SJerome Brunet static unsigned int meson_clk_get_pll_range_m(unsigned long rate,
1538eed1db1SJerome Brunet unsigned long parent_rate,
1548eed1db1SJerome Brunet unsigned int n,
1558eed1db1SJerome Brunet struct meson_clk_pll_data *pll)
1568eed1db1SJerome Brunet {
1578eed1db1SJerome Brunet u64 val = (u64)rate * n;
1588eed1db1SJerome Brunet
1598eed1db1SJerome Brunet if (__pll_round_closest_mult(pll))
1608eed1db1SJerome Brunet return DIV_ROUND_CLOSEST_ULL(val, parent_rate);
1618eed1db1SJerome Brunet
1628eed1db1SJerome Brunet return div_u64(val, parent_rate);
1638eed1db1SJerome Brunet }
1648eed1db1SJerome Brunet
meson_clk_get_pll_range_index(unsigned long rate,unsigned long parent_rate,unsigned int index,unsigned int * m,unsigned int * n,struct meson_clk_pll_data * pll)1658eed1db1SJerome Brunet static int meson_clk_get_pll_range_index(unsigned long rate,
1668eed1db1SJerome Brunet unsigned long parent_rate,
1678eed1db1SJerome Brunet unsigned int index,
1688eed1db1SJerome Brunet unsigned int *m,
1698eed1db1SJerome Brunet unsigned int *n,
1708eed1db1SJerome Brunet struct meson_clk_pll_data *pll)
1718eed1db1SJerome Brunet {
1728eed1db1SJerome Brunet *n = index + 1;
1738eed1db1SJerome Brunet
1748eed1db1SJerome Brunet /* Check the predivider range */
1758eed1db1SJerome Brunet if (*n >= (1 << pll->n.width))
1768eed1db1SJerome Brunet return -EINVAL;
1778eed1db1SJerome Brunet
1788eed1db1SJerome Brunet if (*n == 1) {
1798eed1db1SJerome Brunet /* Get the boundaries out the way */
1808eed1db1SJerome Brunet if (rate <= pll->range->min * parent_rate) {
1818eed1db1SJerome Brunet *m = pll->range->min;
1828eed1db1SJerome Brunet return -ENODATA;
1838eed1db1SJerome Brunet } else if (rate >= pll->range->max * parent_rate) {
1848eed1db1SJerome Brunet *m = pll->range->max;
1858eed1db1SJerome Brunet return -ENODATA;
1868eed1db1SJerome Brunet }
1878eed1db1SJerome Brunet }
1888eed1db1SJerome Brunet
1898eed1db1SJerome Brunet *m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
1908eed1db1SJerome Brunet
1918eed1db1SJerome Brunet /* the pre-divider gives a multiplier too big - stop */
1928eed1db1SJerome Brunet if (*m >= (1 << pll->m.width))
1938eed1db1SJerome Brunet return -EINVAL;
1948eed1db1SJerome Brunet
1958eed1db1SJerome Brunet return 0;
1968eed1db1SJerome Brunet }
1978eed1db1SJerome Brunet
meson_clk_get_pll_get_index(unsigned long rate,unsigned long parent_rate,unsigned int index,unsigned int * m,unsigned int * n,struct meson_clk_pll_data * pll)1988eed1db1SJerome Brunet static int meson_clk_get_pll_get_index(unsigned long rate,
1998eed1db1SJerome Brunet unsigned long parent_rate,
2008eed1db1SJerome Brunet unsigned int index,
2018eed1db1SJerome Brunet unsigned int *m,
2028eed1db1SJerome Brunet unsigned int *n,
2038eed1db1SJerome Brunet struct meson_clk_pll_data *pll)
2048eed1db1SJerome Brunet {
2058eed1db1SJerome Brunet if (pll->range)
2068eed1db1SJerome Brunet return meson_clk_get_pll_range_index(rate, parent_rate,
2078eed1db1SJerome Brunet index, m, n, pll);
2088eed1db1SJerome Brunet else if (pll->table)
2098eed1db1SJerome Brunet return meson_clk_get_pll_table_index(index, m, n, pll);
2108eed1db1SJerome Brunet
2118eed1db1SJerome Brunet return -EINVAL;
2128eed1db1SJerome Brunet }
2138eed1db1SJerome Brunet
meson_clk_get_pll_settings(unsigned long rate,unsigned long parent_rate,unsigned int * best_m,unsigned int * best_n,struct meson_clk_pll_data * pll)2148eed1db1SJerome Brunet static int meson_clk_get_pll_settings(unsigned long rate,
2158eed1db1SJerome Brunet unsigned long parent_rate,
2168eed1db1SJerome Brunet unsigned int *best_m,
2178eed1db1SJerome Brunet unsigned int *best_n,
2188eed1db1SJerome Brunet struct meson_clk_pll_data *pll)
2198eed1db1SJerome Brunet {
220dd601dbcSJerome Brunet unsigned long best = 0, now = 0;
2218eed1db1SJerome Brunet unsigned int i, m, n;
2228eed1db1SJerome Brunet int ret;
2238289aafaSJerome Brunet
2248eed1db1SJerome Brunet for (i = 0, ret = 0; !ret; i++) {
2258eed1db1SJerome Brunet ret = meson_clk_get_pll_get_index(rate, parent_rate,
2268eed1db1SJerome Brunet i, &m, &n, pll);
2278eed1db1SJerome Brunet if (ret == -EINVAL)
2288eed1db1SJerome Brunet break;
2298289aafaSJerome Brunet
2308eed1db1SJerome Brunet now = __pll_params_to_rate(parent_rate, m, n, 0, pll);
2318eed1db1SJerome Brunet if (meson_clk_pll_is_better(rate, best, now, pll)) {
232dd601dbcSJerome Brunet best = now;
2338eed1db1SJerome Brunet *best_m = m;
2348eed1db1SJerome Brunet *best_n = n;
2358eed1db1SJerome Brunet
2368eed1db1SJerome Brunet if (now == rate)
2378eed1db1SJerome Brunet break;
238dd601dbcSJerome Brunet }
2390a1be867SJerome Brunet }
2408289aafaSJerome Brunet
2418eed1db1SJerome Brunet return best ? 0 : -EINVAL;
2427a29a869SCarlo Caione }
2437a29a869SCarlo Caione
meson_clk_pll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)2444cbf0cd6SMartin Blumenstingl static int meson_clk_pll_determine_rate(struct clk_hw *hw,
2454cbf0cd6SMartin Blumenstingl struct clk_rate_request *req)
2467a29a869SCarlo Caione {
247722825dcSJerome Brunet struct clk_regmap *clk = to_clk_regmap(hw);
248722825dcSJerome Brunet struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
2498eed1db1SJerome Brunet unsigned int m, n, frac;
250dd601dbcSJerome Brunet unsigned long round;
2518eed1db1SJerome Brunet int ret;
2527a29a869SCarlo Caione
2534cbf0cd6SMartin Blumenstingl ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,
2544cbf0cd6SMartin Blumenstingl &m, &n, pll);
2558eed1db1SJerome Brunet if (ret)
2564cbf0cd6SMartin Blumenstingl return ret;
257840e1a73SJerome Brunet
2584cbf0cd6SMartin Blumenstingl round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);
259dd601dbcSJerome Brunet
2604cbf0cd6SMartin Blumenstingl if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {
2614cbf0cd6SMartin Blumenstingl req->rate = round;
2624cbf0cd6SMartin Blumenstingl return 0;
2634cbf0cd6SMartin Blumenstingl }
2647a29a869SCarlo Caione
2658289aafaSJerome Brunet /*
2668289aafaSJerome Brunet * The rate provided by the setting is not an exact match, let's
2678289aafaSJerome Brunet * try to improve the result using the fractional parameter
2688289aafaSJerome Brunet */
2694cbf0cd6SMartin Blumenstingl frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);
2704cbf0cd6SMartin Blumenstingl req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);
2717a29a869SCarlo Caione
2724cbf0cd6SMartin Blumenstingl return 0;
2737a29a869SCarlo Caione }
2747a29a869SCarlo Caione
meson_clk_pll_wait_lock(struct clk_hw * hw)275722825dcSJerome Brunet static int meson_clk_pll_wait_lock(struct clk_hw *hw)
276722825dcSJerome Brunet {
277722825dcSJerome Brunet struct clk_regmap *clk = to_clk_regmap(hw);
278722825dcSJerome Brunet struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
27919648dddSHeiner Kallweit int delay = 5000;
280722825dcSJerome Brunet
281722825dcSJerome Brunet do {
28219648dddSHeiner Kallweit /* Is the clock locked now ? Time out after 100ms. */
283722825dcSJerome Brunet if (meson_parm_read(clk->map, &pll->l))
284722825dcSJerome Brunet return 0;
285722825dcSJerome Brunet
28619648dddSHeiner Kallweit udelay(20);
28719648dddSHeiner Kallweit } while (--delay);
288722825dcSJerome Brunet
28945fcbec7SNeil Armstrong return -ETIMEDOUT;
29045fcbec7SNeil Armstrong }
29145fcbec7SNeil Armstrong
meson_clk_pll_is_enabled(struct clk_hw * hw)292d6e81845SMartin Blumenstingl static int meson_clk_pll_is_enabled(struct clk_hw *hw)
293d6e81845SMartin Blumenstingl {
294d6e81845SMartin Blumenstingl struct clk_regmap *clk = to_clk_regmap(hw);
295d6e81845SMartin Blumenstingl struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
296d6e81845SMartin Blumenstingl
29702f1e17cSDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->rst) &&
29802f1e17cSDmitry Rokosov meson_parm_read(clk->map, &pll->rst))
29902f1e17cSDmitry Rokosov return 0;
30002f1e17cSDmitry Rokosov
30102f1e17cSDmitry Rokosov if (!meson_parm_read(clk->map, &pll->en) ||
302d6e81845SMartin Blumenstingl !meson_parm_read(clk->map, &pll->l))
303d6e81845SMartin Blumenstingl return 0;
304d6e81845SMartin Blumenstingl
305d6e81845SMartin Blumenstingl return 1;
306d6e81845SMartin Blumenstingl }
307d6e81845SMartin Blumenstingl
meson_clk_pll_init(struct clk_hw * hw)308*d4c83ac1SDmitry Rokosov static int meson_clk_pll_init(struct clk_hw *hw)
309*d4c83ac1SDmitry Rokosov {
310*d4c83ac1SDmitry Rokosov struct clk_regmap *clk = to_clk_regmap(hw);
311*d4c83ac1SDmitry Rokosov struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
312*d4c83ac1SDmitry Rokosov
313*d4c83ac1SDmitry Rokosov /*
314*d4c83ac1SDmitry Rokosov * Keep the clock running, which was already initialized and enabled
315*d4c83ac1SDmitry Rokosov * from the bootloader stage, to avoid any glitches.
316*d4c83ac1SDmitry Rokosov */
317*d4c83ac1SDmitry Rokosov if ((pll->flags & CLK_MESON_PLL_NOINIT_ENABLED) &&
318*d4c83ac1SDmitry Rokosov meson_clk_pll_is_enabled(hw))
319*d4c83ac1SDmitry Rokosov return 0;
320*d4c83ac1SDmitry Rokosov
321*d4c83ac1SDmitry Rokosov if (pll->init_count) {
322*d4c83ac1SDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->rst))
323*d4c83ac1SDmitry Rokosov meson_parm_write(clk->map, &pll->rst, 1);
324*d4c83ac1SDmitry Rokosov
325*d4c83ac1SDmitry Rokosov regmap_multi_reg_write(clk->map, pll->init_regs,
326*d4c83ac1SDmitry Rokosov pll->init_count);
327*d4c83ac1SDmitry Rokosov
328*d4c83ac1SDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->rst))
329*d4c83ac1SDmitry Rokosov meson_parm_write(clk->map, &pll->rst, 0);
330*d4c83ac1SDmitry Rokosov }
331*d4c83ac1SDmitry Rokosov
332*d4c83ac1SDmitry Rokosov return 0;
333*d4c83ac1SDmitry Rokosov }
334*d4c83ac1SDmitry Rokosov
meson_clk_pcie_pll_enable(struct clk_hw * hw)33539b85002SNeil Armstrong static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
33639b85002SNeil Armstrong {
337d73406edSHeiner Kallweit int retries = 10;
338d73406edSHeiner Kallweit
339d73406edSHeiner Kallweit do {
34039b85002SNeil Armstrong meson_clk_pll_init(hw);
341d73406edSHeiner Kallweit if (!meson_clk_pll_wait_lock(hw))
34239b85002SNeil Armstrong return 0;
343d73406edSHeiner Kallweit pr_info("Retry enabling PCIe PLL clock\n");
344d73406edSHeiner Kallweit } while (--retries);
345d73406edSHeiner Kallweit
346d73406edSHeiner Kallweit return -EIO;
34739b85002SNeil Armstrong }
34839b85002SNeil Armstrong
meson_clk_pll_enable(struct clk_hw * hw)349e40c7e3cSJerome Brunet static int meson_clk_pll_enable(struct clk_hw *hw)
350e40c7e3cSJerome Brunet {
351e40c7e3cSJerome Brunet struct clk_regmap *clk = to_clk_regmap(hw);
352e40c7e3cSJerome Brunet struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
353e40c7e3cSJerome Brunet
354d6e81845SMartin Blumenstingl /* do nothing if the PLL is already enabled */
355d6e81845SMartin Blumenstingl if (clk_hw_is_enabled(hw))
356d6e81845SMartin Blumenstingl return 0;
357d6e81845SMartin Blumenstingl
358e40c7e3cSJerome Brunet /* Make sure the pll is in reset */
35902f1e17cSDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->rst))
360e40c7e3cSJerome Brunet meson_parm_write(clk->map, &pll->rst, 1);
361e40c7e3cSJerome Brunet
362e40c7e3cSJerome Brunet /* Enable the pll */
363e40c7e3cSJerome Brunet meson_parm_write(clk->map, &pll->en, 1);
364e40c7e3cSJerome Brunet
365e40c7e3cSJerome Brunet /* Take the pll out reset */
36602f1e17cSDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->rst))
367e40c7e3cSJerome Brunet meson_parm_write(clk->map, &pll->rst, 0);
368e40c7e3cSJerome Brunet
369b6ec400aSDmitry Rokosov /*
370b6ec400aSDmitry Rokosov * Compared with the previous SoCs, self-adaption current module
371b6ec400aSDmitry Rokosov * is newly added for A1, keep the new power-on sequence to enable the
372b6ec400aSDmitry Rokosov * PLL. The sequence is:
373b6ec400aSDmitry Rokosov * 1. enable the pll, delay for 10us
374b6ec400aSDmitry Rokosov * 2. enable the pll self-adaption current module, delay for 40us
375b6ec400aSDmitry Rokosov * 3. enable the lock detect module
376b6ec400aSDmitry Rokosov */
377b6ec400aSDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->current_en)) {
3786e2acbfeSDmitry Rokosov udelay(10);
379b6ec400aSDmitry Rokosov meson_parm_write(clk->map, &pll->current_en, 1);
3806e2acbfeSDmitry Rokosov udelay(40);
381b8533204SJiapeng Chong }
382b6ec400aSDmitry Rokosov
383b6ec400aSDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
384b6ec400aSDmitry Rokosov meson_parm_write(clk->map, &pll->l_detect, 1);
385b6ec400aSDmitry Rokosov meson_parm_write(clk->map, &pll->l_detect, 0);
386b6ec400aSDmitry Rokosov }
387b6ec400aSDmitry Rokosov
388e40c7e3cSJerome Brunet if (meson_clk_pll_wait_lock(hw))
389e40c7e3cSJerome Brunet return -EIO;
390e40c7e3cSJerome Brunet
391e40c7e3cSJerome Brunet return 0;
392e40c7e3cSJerome Brunet }
393e40c7e3cSJerome Brunet
meson_clk_pll_disable(struct clk_hw * hw)394e40c7e3cSJerome Brunet static void meson_clk_pll_disable(struct clk_hw *hw)
395e40c7e3cSJerome Brunet {
396e40c7e3cSJerome Brunet struct clk_regmap *clk = to_clk_regmap(hw);
397e40c7e3cSJerome Brunet struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
398e40c7e3cSJerome Brunet
399e40c7e3cSJerome Brunet /* Put the pll is in reset */
40002f1e17cSDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->rst))
401e40c7e3cSJerome Brunet meson_parm_write(clk->map, &pll->rst, 1);
402e40c7e3cSJerome Brunet
403e40c7e3cSJerome Brunet /* Disable the pll */
404e40c7e3cSJerome Brunet meson_parm_write(clk->map, &pll->en, 0);
405b6ec400aSDmitry Rokosov
406b6ec400aSDmitry Rokosov /* Disable PLL internal self-adaption current module */
407b6ec400aSDmitry Rokosov if (MESON_PARM_APPLICABLE(&pll->current_en))
408b6ec400aSDmitry Rokosov meson_parm_write(clk->map, &pll->current_en, 0);
409e40c7e3cSJerome Brunet }
410e40c7e3cSJerome Brunet
meson_clk_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)4117a29a869SCarlo Caione static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
4127a29a869SCarlo Caione unsigned long parent_rate)
4137a29a869SCarlo Caione {
414722825dcSJerome Brunet struct clk_regmap *clk = to_clk_regmap(hw);
415722825dcSJerome Brunet struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
4169e717285SMartin Blumenstingl unsigned int enabled, m, n, frac = 0;
4177a29a869SCarlo Caione unsigned long old_rate;
4189e717285SMartin Blumenstingl int ret;
4197a29a869SCarlo Caione
4207a29a869SCarlo Caione if (parent_rate == 0 || rate == 0)
4217a29a869SCarlo Caione return -EINVAL;
4227a29a869SCarlo Caione
4232f290b7cSMartin Blumenstingl old_rate = clk_hw_get_rate(hw);
4247a29a869SCarlo Caione
4258eed1db1SJerome Brunet ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
4268eed1db1SJerome Brunet if (ret)
4278eed1db1SJerome Brunet return ret;
4287a29a869SCarlo Caione
429e40c7e3cSJerome Brunet enabled = meson_parm_read(clk->map, &pll->en);
430e40c7e3cSJerome Brunet if (enabled)
431e40c7e3cSJerome Brunet meson_clk_pll_disable(hw);
43245fcbec7SNeil Armstrong
4338eed1db1SJerome Brunet meson_parm_write(clk->map, &pll->n, n);
4348eed1db1SJerome Brunet meson_parm_write(clk->map, &pll->m, m);
4357a29a869SCarlo Caione
4368289aafaSJerome Brunet if (MESON_PARM_APPLICABLE(&pll->frac)) {
4378eed1db1SJerome Brunet frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
4388289aafaSJerome Brunet meson_parm_write(clk->map, &pll->frac, frac);
4398289aafaSJerome Brunet }
4407a29a869SCarlo Caione
441e40c7e3cSJerome Brunet /* If the pll is stopped, bail out now */
442e40c7e3cSJerome Brunet if (!enabled)
443e40c7e3cSJerome Brunet return 0;
4444a472951SMichael Turquette
445ccdc1f08SMartin Blumenstingl ret = meson_clk_pll_enable(hw);
446ccdc1f08SMartin Blumenstingl if (ret) {
44716182ac3SDmitry Rokosov pr_warn("%s: pll %s didn't lock, trying to set old rate %lu\n",
44816182ac3SDmitry Rokosov __func__, clk_hw_get_name(hw), old_rate);
449722825dcSJerome Brunet /*
450722825dcSJerome Brunet * FIXME: Do we really need/want this HACK ?
451722825dcSJerome Brunet * It looks unsafe. what happens if the clock gets into a
452722825dcSJerome Brunet * broken state and we can't lock back on the old_rate ? Looks
453722825dcSJerome Brunet * like an infinite recursion is possible
454722825dcSJerome Brunet */
4557a29a869SCarlo Caione meson_clk_pll_set_rate(hw, old_rate, parent_rate);
4567a29a869SCarlo Caione }
4577a29a869SCarlo Caione
458ccdc1f08SMartin Blumenstingl return ret;
4597a29a869SCarlo Caione }
4607a29a869SCarlo Caione
46139b85002SNeil Armstrong /*
46239b85002SNeil Armstrong * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
46339b85002SNeil Armstrong * 100MHz reference clock for the PCIe Analog PHY, and thus requires
46439b85002SNeil Armstrong * a strict register sequence to enable the PLL.
46539b85002SNeil Armstrong * To simplify, re-use the _init() op to enable the PLL and keep
46639b85002SNeil Armstrong * the other ops except set_rate since the rate is fixed.
46739b85002SNeil Armstrong */
46839b85002SNeil Armstrong const struct clk_ops meson_clk_pcie_pll_ops = {
46939b85002SNeil Armstrong .recalc_rate = meson_clk_pll_recalc_rate,
4704cbf0cd6SMartin Blumenstingl .determine_rate = meson_clk_pll_determine_rate,
47139b85002SNeil Armstrong .is_enabled = meson_clk_pll_is_enabled,
47239b85002SNeil Armstrong .enable = meson_clk_pcie_pll_enable,
47339b85002SNeil Armstrong .disable = meson_clk_pll_disable
47439b85002SNeil Armstrong };
47539b85002SNeil Armstrong EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
47639b85002SNeil Armstrong
477ec623f2aSMichael Turquette const struct clk_ops meson_clk_pll_ops = {
478722825dcSJerome Brunet .init = meson_clk_pll_init,
4797a29a869SCarlo Caione .recalc_rate = meson_clk_pll_recalc_rate,
4804cbf0cd6SMartin Blumenstingl .determine_rate = meson_clk_pll_determine_rate,
4817a29a869SCarlo Caione .set_rate = meson_clk_pll_set_rate,
482d6e81845SMartin Blumenstingl .is_enabled = meson_clk_pll_is_enabled,
483e40c7e3cSJerome Brunet .enable = meson_clk_pll_enable,
484e40c7e3cSJerome Brunet .disable = meson_clk_pll_disable
4857a29a869SCarlo Caione };
486889c2b7eSJerome Brunet EXPORT_SYMBOL_GPL(meson_clk_pll_ops);
4877a29a869SCarlo Caione
488ec623f2aSMichael Turquette const struct clk_ops meson_clk_pll_ro_ops = {
4897a29a869SCarlo Caione .recalc_rate = meson_clk_pll_recalc_rate,
490d6e81845SMartin Blumenstingl .is_enabled = meson_clk_pll_is_enabled,
4917a29a869SCarlo Caione };
492889c2b7eSJerome Brunet EXPORT_SYMBOL_GPL(meson_clk_pll_ro_ops);
493889c2b7eSJerome Brunet
494889c2b7eSJerome Brunet MODULE_DESCRIPTION("Amlogic PLL driver");
495889c2b7eSJerome Brunet MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
496889c2b7eSJerome Brunet MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
497e0892cb4SNeil Armstrong MODULE_LICENSE("GPL");
498