Lines Matching +full:pll +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
103 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
104 vco_out->pdiv = 1; in pll_calc_param()
106 vco_out->rate = vco_out->ndiv_int * parent_rate; in pll_calc_param()
107 residual = (u64)vco_out->ndiv_frac * (u64)parent_rate; in pll_calc_param()
109 vco_out->rate += residual; in pll_calc_param()
118 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
122 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
123 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
126 if (i >= pll->num_vco_entries) in pll_get_rate_index()
127 return -EINVAL; in pll_get_rate_index()
137 return -EINVAL; in get_kp()
144 return -EINVAL; in get_kp()
147 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
150 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
153 u32 val = readl(pll->status_base + ctrl->status.offset); in pll_wait_for_lock()
155 if (val & (1 << ctrl->status.shift)) in pll_wait_for_lock()
160 return -EIO; in pll_wait_for_lock()
163 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, in iproc_pll_write() argument
166 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_write()
170 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && in iproc_pll_write()
171 (base == pll->status_base || base == pll->control_base))) in iproc_pll_write()
175 static void __pll_disable(struct iproc_pll *pll) in __pll_disable() argument
177 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in __pll_disable()
180 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { in __pll_disable()
181 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_disable()
182 val &= ~(1 << ctrl->asiu.en_shift); in __pll_disable()
183 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_disable()
186 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { in __pll_disable()
187 val = readl(pll->control_base + ctrl->aon.offset); in __pll_disable()
188 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_disable()
189 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_disable()
192 if (pll->pwr_base) { in __pll_disable()
194 val = readl(pll->pwr_base + ctrl->aon.offset); in __pll_disable()
195 val |= 1 << ctrl->aon.iso_shift; in __pll_disable()
196 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
199 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_disable()
200 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
204 static int __pll_enable(struct iproc_pll *pll) in __pll_enable() argument
206 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in __pll_enable()
209 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { in __pll_enable()
210 val = readl(pll->control_base + ctrl->aon.offset); in __pll_enable()
211 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_enable()
212 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_enable()
215 if (pll->pwr_base) { in __pll_enable()
216 /* power up the PLL and make sure it's not latched */ in __pll_enable()
217 val = readl(pll->pwr_base + ctrl->aon.offset); in __pll_enable()
218 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_enable()
219 val &= ~(1 << ctrl->aon.iso_shift); in __pll_enable()
220 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_enable()
224 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { in __pll_enable()
225 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_enable()
226 val |= (1 << ctrl->asiu.en_shift); in __pll_enable()
227 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_enable()
233 static void __pll_put_in_reset(struct iproc_pll *pll) in __pll_put_in_reset() argument
236 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in __pll_put_in_reset()
237 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; in __pll_put_in_reset() local
239 val = readl(pll->control_base + reset->offset); in __pll_put_in_reset()
240 if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW) in __pll_put_in_reset()
241 val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); in __pll_put_in_reset()
243 val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); in __pll_put_in_reset()
244 iproc_pll_write(pll, pll->control_base, reset->offset, val); in __pll_put_in_reset()
247 static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, in __pll_bring_out_reset() argument
251 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in __pll_bring_out_reset()
252 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; in __pll_bring_out_reset() local
253 const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; in __pll_bring_out_reset()
255 val = readl(pll->control_base + dig_filter->offset); in __pll_bring_out_reset()
256 val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | in __pll_bring_out_reset()
257 bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | in __pll_bring_out_reset()
258 bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); in __pll_bring_out_reset()
259 val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | in __pll_bring_out_reset()
260 ka << dig_filter->ka_shift; in __pll_bring_out_reset()
261 iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); in __pll_bring_out_reset()
263 val = readl(pll->control_base + reset->offset); in __pll_bring_out_reset()
264 if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW) in __pll_bring_out_reset()
265 val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); in __pll_bring_out_reset()
267 val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); in __pll_bring_out_reset()
268 iproc_pll_write(pll, pll->control_base, reset->offset, val); in __pll_bring_out_reset()
272 * Determines if the change to be applied to the PLL is minor (just an update
274 * disruptive reset and lock sequence.
276 static bool pll_fractional_change_only(struct iproc_pll *pll, in pll_fractional_change_only() argument
279 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_fractional_change_only()
284 /* PLL needs to be locked */ in pll_fractional_change_only()
285 val = readl(pll->status_base + ctrl->status.offset); in pll_fractional_change_only()
286 if ((val & (1 << ctrl->status.shift)) == 0) in pll_fractional_change_only()
289 val = readl(pll->control_base + ctrl->ndiv_int.offset); in pll_fractional_change_only()
290 ndiv_int = (val >> ctrl->ndiv_int.shift) & in pll_fractional_change_only()
291 bit_mask(ctrl->ndiv_int.width); in pll_fractional_change_only()
293 if (ndiv_int != vco->ndiv_int) in pll_fractional_change_only()
296 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_fractional_change_only()
297 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); in pll_fractional_change_only()
299 if (pdiv != vco->pdiv) in pll_fractional_change_only()
308 struct iproc_pll *pll = clk->pll; in pll_set_rate() local
309 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_set_rate()
311 unsigned long rate = vco->rate; in pll_set_rate()
315 const char *clk_name = clk_hw_get_name(&clk->hw); in pll_set_rate()
321 if (vco->pdiv == 0) in pll_set_rate()
324 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
337 pr_err("%s: pll: %s has invalid rate: %lu\n", __func__, in pll_set_rate()
339 return -EINVAL; in pll_set_rate()
344 pr_err("%s: pll: %s has invalid kp\n", __func__, clk_name); in pll_set_rate()
348 ret = __pll_enable(pll); in pll_set_rate()
350 pr_err("%s: pll: %s fails to enable\n", __func__, clk_name); in pll_set_rate()
354 if (pll_fractional_change_only(clk->pll, vco)) { in pll_set_rate()
356 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { in pll_set_rate()
357 val = readl(pll->control_base + ctrl->ndiv_frac.offset); in pll_set_rate()
358 val &= ~(bit_mask(ctrl->ndiv_frac.width) << in pll_set_rate()
359 ctrl->ndiv_frac.shift); in pll_set_rate()
360 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; in pll_set_rate()
361 iproc_pll_write(pll, pll->control_base, in pll_set_rate()
362 ctrl->ndiv_frac.offset, val); in pll_set_rate()
367 /* put PLL in reset */ in pll_set_rate()
368 __pll_put_in_reset(pll); in pll_set_rate()
370 /* set PLL in user mode before modifying PLL controls */ in pll_set_rate()
371 if (ctrl->flags & IPROC_CLK_PLL_USER_MODE_ON) { in pll_set_rate()
372 val = readl(pll->control_base + ctrl->macro_mode.offset); in pll_set_rate()
373 val &= ~(bit_mask(ctrl->macro_mode.width) << in pll_set_rate()
374 ctrl->macro_mode.shift); in pll_set_rate()
375 val |= PLL_USER_MODE << ctrl->macro_mode.shift; in pll_set_rate()
376 iproc_pll_write(pll, pll->control_base, in pll_set_rate()
377 ctrl->macro_mode.offset, val); in pll_set_rate()
380 iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0); in pll_set_rate()
382 val = readl(pll->control_base + ctrl->vco_ctrl.l_offset); in pll_set_rate()
392 iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val); in pll_set_rate()
395 val = readl(pll->control_base + ctrl->ndiv_int.offset); in pll_set_rate()
396 val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); in pll_set_rate()
397 val |= vco->ndiv_int << ctrl->ndiv_int.shift; in pll_set_rate()
398 iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val); in pll_set_rate()
401 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { in pll_set_rate()
402 val = readl(pll->control_base + ctrl->ndiv_frac.offset); in pll_set_rate()
403 val &= ~(bit_mask(ctrl->ndiv_frac.width) << in pll_set_rate()
404 ctrl->ndiv_frac.shift); in pll_set_rate()
405 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; in pll_set_rate()
406 iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset, in pll_set_rate()
411 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_set_rate()
412 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); in pll_set_rate()
413 val |= vco->pdiv << ctrl->pdiv.shift; in pll_set_rate()
414 iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val); in pll_set_rate()
416 __pll_bring_out_reset(pll, kp, ka, ki); in pll_set_rate()
418 ret = pll_wait_for_lock(pll); in pll_set_rate()
420 pr_err("%s: pll: %s failed to lock\n", __func__, clk_name); in pll_set_rate()
430 struct iproc_pll *pll = clk->pll; in iproc_pll_enable() local
432 return __pll_enable(pll); in iproc_pll_enable()
438 struct iproc_pll *pll = clk->pll; in iproc_pll_disable() local
439 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_disable()
441 if (ctrl->flags & IPROC_CLK_AON) in iproc_pll_disable()
444 __pll_disable(pll); in iproc_pll_disable()
451 struct iproc_pll *pll = clk->pll; in iproc_pll_recalc_rate() local
452 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_recalc_rate()
461 /* PLL needs to be locked */ in iproc_pll_recalc_rate()
462 val = readl(pll->status_base + ctrl->status.offset); in iproc_pll_recalc_rate()
463 if ((val & (1 << ctrl->status.shift)) == 0) in iproc_pll_recalc_rate()
467 * PLL output frequency = in iproc_pll_recalc_rate()
471 val = readl(pll->control_base + ctrl->ndiv_int.offset); in iproc_pll_recalc_rate()
472 ndiv_int = (val >> ctrl->ndiv_int.shift) & in iproc_pll_recalc_rate()
473 bit_mask(ctrl->ndiv_int.width); in iproc_pll_recalc_rate()
476 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { in iproc_pll_recalc_rate()
477 val = readl(pll->control_base + ctrl->ndiv_frac.offset); in iproc_pll_recalc_rate()
478 ndiv_frac = (val >> ctrl->ndiv_frac.shift) & in iproc_pll_recalc_rate()
479 bit_mask(ctrl->ndiv_frac.width); in iproc_pll_recalc_rate()
483 val = readl(pll->control_base + ctrl->pdiv.offset); in iproc_pll_recalc_rate()
484 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); in iproc_pll_recalc_rate()
501 struct iproc_pll *pll = clk->pll; in iproc_pll_determine_rate() local
502 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_determine_rate()
507 if (req->rate == 0 || req->best_parent_rate == 0) in iproc_pll_determine_rate()
508 return -EINVAL; in iproc_pll_determine_rate()
510 if (ctrl->flags & IPROC_CLK_PLL_CALC_PARAM) { in iproc_pll_determine_rate()
513 ret = pll_calc_param(req->rate, req->best_parent_rate, in iproc_pll_determine_rate()
518 req->rate = vco_param.rate; in iproc_pll_determine_rate()
522 if (!pll->vco_param) in iproc_pll_determine_rate()
523 return -EINVAL; in iproc_pll_determine_rate()
526 for (i = 0; i < pll->num_vco_entries; i++) { in iproc_pll_determine_rate()
527 diff = abs(req->rate - pll->vco_param[i].rate); in iproc_pll_determine_rate()
537 req->rate = pll->vco_param[best_idx].rate; in iproc_pll_determine_rate()
546 struct iproc_pll *pll = clk->pll; in iproc_pll_set_rate() local
547 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_set_rate()
551 if (ctrl->flags & IPROC_CLK_PLL_CALC_PARAM) { in iproc_pll_set_rate()
556 rate_index = pll_get_rate_index(pll, rate); in iproc_pll_set_rate()
560 vco_param = pll->vco_param[rate_index]; in iproc_pll_set_rate()
578 const struct iproc_clk_ctrl *ctrl = clk->ctrl; in iproc_clk_enable()
579 struct iproc_pll *pll = clk->pll; in iproc_clk_enable() local
583 val = readl(pll->control_base + ctrl->enable.offset); in iproc_clk_enable()
584 val &= ~(1 << ctrl->enable.enable_shift); in iproc_clk_enable()
585 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); in iproc_clk_enable()
588 val = readl(pll->control_base + ctrl->enable.offset); in iproc_clk_enable()
589 val &= ~(1 << ctrl->enable.hold_shift); in iproc_clk_enable()
590 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); in iproc_clk_enable()
598 const struct iproc_clk_ctrl *ctrl = clk->ctrl; in iproc_clk_disable()
599 struct iproc_pll *pll = clk->pll; in iproc_clk_disable() local
602 if (ctrl->flags & IPROC_CLK_AON) in iproc_clk_disable()
605 val = readl(pll->control_base + ctrl->enable.offset); in iproc_clk_disable()
606 val |= 1 << ctrl->enable.enable_shift; in iproc_clk_disable()
607 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); in iproc_clk_disable()
614 const struct iproc_clk_ctrl *ctrl = clk->ctrl; in iproc_clk_recalc_rate()
615 struct iproc_pll *pll = clk->pll; in iproc_clk_recalc_rate() local
623 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_recalc_rate()
624 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); in iproc_clk_recalc_rate()
628 if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2) in iproc_clk_recalc_rate()
641 if (req->rate == 0) in iproc_clk_determine_rate()
642 return -EINVAL; in iproc_clk_determine_rate()
643 if (req->rate == req->best_parent_rate) in iproc_clk_determine_rate()
646 bestdiv = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate); in iproc_clk_determine_rate()
648 req->rate = req->best_parent_rate; in iproc_clk_determine_rate()
653 req->rate = req->best_parent_rate / bestdiv; in iproc_clk_determine_rate()
662 const struct iproc_clk_ctrl *ctrl = clk->ctrl; in iproc_clk_set_rate()
663 struct iproc_pll *pll = clk->pll; in iproc_clk_set_rate() local
668 return -EINVAL; in iproc_clk_set_rate()
671 if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2) in iproc_clk_set_rate()
675 return -EINVAL; in iproc_clk_set_rate()
677 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_set_rate()
679 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
681 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
682 val |= div << ctrl->mdiv.shift; in iproc_clk_set_rate()
684 iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val); in iproc_clk_set_rate()
698 * Some PLLs require the PLL SW override bit to be set before changes can be
699 * applied to the PLL
701 static void iproc_pll_sw_cfg(struct iproc_pll *pll) in iproc_pll_sw_cfg() argument
703 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_sw_cfg()
705 if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) { in iproc_pll_sw_cfg()
708 val = readl(pll->control_base + ctrl->sw_ctrl.offset); in iproc_pll_sw_cfg()
709 val |= BIT(ctrl->sw_ctrl.shift); in iproc_pll_sw_cfg()
710 iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset, in iproc_pll_sw_cfg()
723 struct iproc_pll *pll; in iproc_pll_clk_setup() local
734 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in iproc_pll_clk_setup()
735 if (WARN_ON(!pll)) in iproc_pll_clk_setup()
741 clk_data->num = num_clks; in iproc_pll_clk_setup()
747 pll->control_base = of_iomap(node, 0); in iproc_pll_clk_setup()
748 if (WARN_ON(!pll->control_base)) in iproc_pll_clk_setup()
752 pll->pwr_base = of_iomap(node, 1); in iproc_pll_clk_setup()
755 if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { in iproc_pll_clk_setup()
756 pll->asiu_base = of_iomap(node, 2); in iproc_pll_clk_setup()
757 if (WARN_ON(!pll->asiu_base)) in iproc_pll_clk_setup()
761 if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) { in iproc_pll_clk_setup()
765 pll->status_base = of_iomap(node, 2); in iproc_pll_clk_setup()
766 if (!pll->status_base) in iproc_pll_clk_setup()
769 pll->status_base = pll->control_base; in iproc_pll_clk_setup()
771 /* initialize and register the PLL itself */ in iproc_pll_clk_setup()
772 pll->ctrl = pll_ctrl; in iproc_pll_clk_setup()
775 iclk->pll = pll; in iproc_pll_clk_setup()
777 ret = of_property_read_string_index(node, "clock-output-names", in iproc_pll_clk_setup()
788 iclk->hw.init = &init; in iproc_pll_clk_setup()
791 pll->num_vco_entries = num_vco_entries; in iproc_pll_clk_setup()
792 pll->vco_param = vco; in iproc_pll_clk_setup()
795 iproc_pll_sw_cfg(pll); in iproc_pll_clk_setup()
797 ret = clk_hw_register(NULL, &iclk->hw); in iproc_pll_clk_setup()
801 clk_data->hws[0] = &iclk->hw; in iproc_pll_clk_setup()
808 ret = of_property_read_string_index(node, "clock-output-names", in iproc_pll_clk_setup()
814 iclk->pll = pll; in iproc_pll_clk_setup()
815 iclk->ctrl = &clk_ctrl[i]; in iproc_pll_clk_setup()
822 iclk->hw.init = &init; in iproc_pll_clk_setup()
824 ret = clk_hw_register(NULL, &iclk->hw); in iproc_pll_clk_setup()
828 clk_data->hws[i] = &iclk->hw; in iproc_pll_clk_setup()
838 while (--i >= 0) in iproc_pll_clk_setup()
839 clk_hw_unregister(clk_data->hws[i]); in iproc_pll_clk_setup()
842 if (pll->status_base != pll->control_base) in iproc_pll_clk_setup()
843 iounmap(pll->status_base); in iproc_pll_clk_setup()
846 if (pll->asiu_base) in iproc_pll_clk_setup()
847 iounmap(pll->asiu_base); in iproc_pll_clk_setup()
850 if (pll->pwr_base) in iproc_pll_clk_setup()
851 iounmap(pll->pwr_base); in iproc_pll_clk_setup()
853 iounmap(pll->control_base); in iproc_pll_clk_setup()
862 kfree(pll); in iproc_pll_clk_setup()