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/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
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H A Dfsl,qoriq-clock-legacy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
24 - fsl,qoriq-core-mux-1.0
25 - fsl,qoriq-core-mux-2.0
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H A Dcalxeda.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda highbank platform Clock Controller
13 "hb-sregs" node.
16 - Andre Przywara <andre.przywara@arm.com>
19 "#clock-cells":
24 - calxeda,hb-pll-clock
25 - calxeda,hb-a9periph-clock
26 - calxeda,hb-a9bus-clock
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/linux/drivers/clk/davinci/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 * PLL clock driver for TI Davinci SoCs
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
28 #include "pll.h"
78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
85 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
89 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
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/linux/sound/soc/intel/boards/
H A Dcht_bsw_rt5672.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
22 #include <sound/soc-acpi.h>
24 #include "../atom/sst-atom-controls.h"
25 #include "../common/soc-intel-quirks.h"
28 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
30 #define CHT_CODEC_DAI "rt5670-aif1"
54 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
55 struct snd_soc_card *card = dapm->card; in platform_clock_control()
62 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
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H A Dsof_da7219.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/soc-acpi.h>
21 /* Driver-specific board quirks: from bit 0 to 7 */
27 #define DIALOG_CODEC_DAI "da7219-hifi"
32 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
33 struct snd_soc_card *card = dapm->card; in platform_clock_control()
38 if (ctx->da7219.pll_bypass) in platform_clock_control()
41 /* PLL SRM mode */ in platform_clock_control()
44 dev_err(card->dev, "Codec dai not found; Unable to set/unset codec pll\n"); in platform_clock_control()
45 return -EIO; in platform_clock_control()
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H A Dbytcr_wm5102.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bytcr_wm5102.c - ASoc Machine driver for Intel Baytrail platforms with a
8 * Copyright (C) 2014-2020 Intel Corp
27 #include <sound/soc-acpi.h>
29 #include "../atom/sst-atom-controls.h"
51 /* Note these values are pre-shifte
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H A Dbytcht_da7213.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bytcht-da7213.c - ASoc Machine driver for Intel Baytrail and
4 * Cherrytrail-based platforms, with Dialog DA7213 codec
7 * Author: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
21 #include <sound/soc-acpi.h>
23 #include "../atom/sst-atom-controls.h"
46 /* Assume Mic1 is linked to Headset and Mic2 to on-board mic */
50 /* SOC-codec link */
70 rate->min = rate->max = 48000; in codec_fixup()
71 channels->min = channels->max = 2; in codec_fixup()
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/linux/Documentation/driver-api/
H A Dsm501.rst15 ----
23 chips via the platform device and driver system.
26 be specified by the platform data) and then exports the selected
27 peripheral set as platform devices for the specific drivers.
29 The core re-uses the platform device system as the platform device
31 need to create a new bus-type and the associated code to go with it.
35 ---------
43 as this is by-far the most resource-sensitive of the on-chip functions.
59 -------------
61 The platform device driver uses a set of platform data to pass
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/linux/drivers/clk/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 by platform/architecture code. This method is deprecated. Modern
46 bool "PLL Driver for HSDK platform"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
87 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
91 tristate "Raspberry Pi RP1-based clock support"
96 This multi-function device has 3 main PLLs and several clock
97 generators to drive the internal sub-peripherals.
106 multi-function device has one fixed-rate oscillator, clocked
137 be pre-programmed to support other configurations and features not yet
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H A Dclk-qoriq.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
14 #include <linux/clk-provider.h>
34 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
49 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
53 int pll; /* CGx_PLLn */ member
69 * cmux freq must be >= platform pll.
70 * If not set, cmux freq must be >= platform pll/2
83 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
84 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
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/linux/sound/soc/intel/avs/boards/
H A Dda7219.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation
15 #include <sound/soc-acpi.h>
16 #include <sound/soc-dapm.h>
17 #include <uapi/linux/input-event-codes.h>
21 #define DA7219_DAI_NAME "da7219-hif
171 struct snd_soc_dai_link_component *platform; avs_create_dai_link() local
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/linux/drivers/clk/meson/
H A Da1-pll.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
13 #include "clk-pll.h"
14 #include "clk-regmap.h"
15 #include "meson-clkc-utils.h"
27 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
178 * and is required by the platform to operate correctly.
182 * b) CCF has a clock hand-off mechanism to make the sure the
216 * and is required by the platform to operate correctly.
249 * and is required by the platform to operate correctly.
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/linux/drivers/clk/sophgo/
H A Dclk-sg2044-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2044 PLL clock controller driver
13 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
57 for (_var = (_limit)->min; _var <= (_limit)->max; _var++)
85 struct sg2044_pll_internal pll; member
90 struct sg2044_clk_common * const *pll; member
107 return value >= limit->min && value <= limit->max; in sg2044_clk_fit_limit()
142 struct sg2044_pll *pll = hw_to_sg2044_pll(hw); in sg2044_pll_recalc_rate() local
146 ret = regmap_read(pll->common.regmap, in sg2044_pll_recalc_rate()
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/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Intel(R) Dynamic Platform and Thermal Framework Sysfs Interface
12 ------------
14 Intel(R) Dynamic Platform and Thermal Framework (DPTF) is a platform
21 Since it is a platform level framework, this has several components.
26 "Linux Thermal Daemon" to read platform specific thermal and power
31 ----------------------------
33 :file:`/sys/bus/platform/devices/<N>/uuids`, where <N>
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
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/linux/include/linux/platform_data/
H A Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
34 * enum si5351_clkout_src - Si5351 clock output clock source
51 * enum si5351_drive_strength - Si5351 clock output drive strength
67 * enum si5351_disable_state - Si5351 clock output disable state
84 * struct si5351_clkout_config - Si5351 clock output configuration
88 * @pll_master: if true, clkout can also change pll rate
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/linux/arch/arm/boot/dts/vt8500/
H A Dwm8850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
21 next-level-cache = <&l2_cache>;
33 #address-cells = <1>;
34 #size-cells = <1>;
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H A Dwm8750.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "simple-bus";
40 interrupt-parent = <&intc0>;
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/linux/include/media/i2c/
H A Dadv7343.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
16 * struct adv7343_power_mode - power mode configuration.
18 * level. All DACs and the internal PLL circuit are disabled.
20 * @pll_control: PLL and oversampling control. This control allows internal
21 * PLL 1 circuit to be powered down and the oversampling to be
28 * [1] http://www.analog.com/static/imported-files/data_sheets/ADV7342_7343.pdf
37 * struct adv7343_sd_config - SD Only Output Configuration.
46 * struct adv7343_platform_data - Platform data values and access functions.
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,edp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides
20 - enum:
21 - qcom,sa8775p-edp-phy
22 - qcom,sc7280-edp-phy
23 - qcom,sc8180x-edp-phy
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/linux/drivers/firmware/xilinx/
H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
28 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/firmware/xlnx-event-manager.h>
30 #include "zynqmp-debug.h"
37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
54 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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/linux/drivers/platform/x86/intel/pmc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # Intel x86 Platform-Specific Drivers
13 The Intel Platform Controller Hub for Intel Core SoCs provides access
21 - SLP_S0_RESIDENCY counter
22 - PCH IP Power Gating status
23 - LTR Ignore / LTR Show
24 - MPHY/PLL gating status (Sunrisepoint PCH only)
25 - SLPS0 Debug registers (Cannonlake/Icelake PCH)
26 - Low Power Mode registers (Tigerlake and beyond)
27 - PMC quirks as needed to enable SLPS0/S0ix
/linux/drivers/video/fbdev/via/
H A Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 * clock and PLL management functions
12 #include <linux/via-core.h>
19 "releasing full documentation for your platform!\n";
21 static inline u32 cle266_encode_pll(struct via_pll_config pll) in cle266_encode_pll() argument
23 return (pll.multiplier << 8) in cle266_encode_pll()
24 | (pll.rshift << 6) in cle266_encode_pll()
25 | pll.divisor; in cle266_encode_pll()
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/linux/drivers/clk/qcom/
H A Dapcs-sdx55.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
19 #include "clk-regmap.h"
20 #include "clk-regmap-mux-div.h"
27 { .fw_name = "pll" },
32 * (mux and divider), while the A7 PLL is reconfigured.
50 struct device *dev = &pdev->dev; in qcom_apcs_sdx55_clk_probe()
51 struct device *parent = dev->parent; in qcom_apcs_sdx55_clk_probe()
61 return -ENODEV; in qcom_apcs_sdx55_clk_probe()
66 return -ENOMEM; in qcom_apcs_sdx55_clk_probe()
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/linux/sound/soc/amd/
H A Dacp-da7219-max98357a.c1 // SPDX-License-Identifier: MIT
5 //Copyright 2017-2021 Advanced Micro Devices, Inc.
11 #include <sound/soc-dapm.h>
56 struct snd_soc_card *card = rtd->card; in cz_da7219_init()
58 struct snd_soc_component *component = codec_dai->component; in cz_da7219_init()
60 dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name); in cz_da7219_init()
65 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret); in cz_da7219_init()
72 dev_err(rtd->dev, "can't set codec pll: %d\n", ret); in cz_da7219_init()
76 da7219_dai_wclk = devm_clk_get(component->dev, "da7219-dai-wclk"); in cz_da7219_init()
80 da7219_dai_bclk = devm_clk_get(component->dev, "da7219-dai-bclk"); in cz_da7219_init()
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