Lines Matching +full:platform +full:- +full:pll
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
39 - fsl,p3041-clockgen
40 - fsl,p4080-clockgen
41 - fsl,p5020-clockgen
42 - fsl,p5040-clockgen
43 - const: fsl,qoriq-clockgen-1.0
44 - items:
45 - enum:
46 - fsl,t1023-clockgen
47 - fsl,t1024-clockgen
48 - fsl,t1040-clockgen
49 - fsl,t1042-clockgen
50 - fsl,t2080-clockgen
51 - fsl,t2081-clockgen
52 - fsl,t4240-clockgen
53 - const: fsl,qoriq-clockgen-2.0
54 - items:
55 - enum:
56 - fsl,b4420-clockgen
57 - fsl,b4860-clockgen
58 - const: fsl,b4-clockgen
59 - items:
60 - enum:
61 - fsl,ls1012a-clockgen
62 - fsl,ls1021a-clockgen
63 - fsl,ls1028a-clockgen
64 - fsl,ls1043a-clockgen
65 - fsl,ls1046a-clockgen
66 - fsl,ls1088a-clockgen
67 - fsl,ls2080a-clockgen
68 - fsl,lx2160a-clockgen
75 '#address-cells':
78 '#size-cells':
81 '#clock-cells':
92 4 platform pll n=pll/(n+1). For example, when n=1,
96 clock-frequency:
101 - description:
102 sysclk may be provided as an input clock. Either clock-frequency
104 - description:
107 platform PLL.
110 clock-names:
112 - const: sysclk
113 - const: coreclk
116 '^mux[0-9]@[a-f0-9]+$':
118 $ref: fsl,qoriq-clock-legacy.yaml
120 '^sysclk(-[a-z0-9]+)?$':
122 $ref: fsl,qoriq-clock-legacy.yaml
124 '^pll[0-9]@[a-f0-9]+$':
126 $ref: fsl,qoriq-clock-legacy.yaml
128 '^platform\-pll@[a-f0-9]+$':
130 $ref: fsl,qoriq-clock-legacy.yaml
133 - compatible
134 - reg
135 - '#clock-cells'
140 - |
142 global-utilities@e1000 {
143 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
145 clock-frequency = <133333333>;
146 #clock-cells = <2>;
149 - |
151 global-utilities@e1000 {
152 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
155 clock-frequency = <133333333>;
156 #address-cells = <1>;
157 #size-cells = <1>;
158 #clock-cells = <2>;
161 compatible = "fsl,qoriq-sysclk-1.0";
162 clock-output-names = "sysclk";
163 #clock-cells = <0>;
167 compatible = "fsl,qoriq-core-pll-1.0";
169 #clock-cells = <1>;
171 clock-output-names = "pll0", "pll0-div2";
175 compatible = "fsl,qoriq-core-pll-1.0";
177 #clock-cells = <1>;
179 clock-output-names = "pll1", "pll1-div2";
183 compatible = "fsl,qoriq-core-mux-1.0";
185 #clock-cells = <0>;
187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clock-output-names = "cmux0";
192 compatible = "fsl,qoriq-core-mux-1.0";
194 #clock-cells = <0>;
196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
197 clock-output-names = "cmux1";
200 platform-pll@c00 {
201 #clock-cells = <1>;
203 compatible = "fsl,qoriq-platform-pll-1.0";
205 clock-output-names = "platform-pll", "platform-pll-div2";