Lines Matching +full:platform +full:- +full:pll
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <0>;
15 #size-cells = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "simple-bus";
44 interrupt-parent = <&intc0>;
46 intc0: interrupt-controller@d8140000 {
47 compatible = "via,vt8500-intc";
48 interrupt-controller;
50 #interrupt-cells = <1>;
54 intc1: interrupt-controller@d8150000 {
55 compatible = "via,vt8500-intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
63 compatible = "wm,wm8750-pinctrl";
65 interrupt-controller;
66 #interrupt-cells = <2>;
67 gpio-controller;
68 #gpio-cells = <2>;
72 compatible = "via,vt8500-pmc";
76 #address-cells = <1>;
77 #size-cells = <0>;
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 clock-frequency = <24000000>;
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 clock-frequency = <25000000>;
92 #clock-cells = <0>;
93 compatible = "wm,wm8750-pll-clock";
99 #clock-cells = <0>;
100 compatible = "wm,wm8750-pll-clock";
106 #clock-cells = <0>;
107 compatible = "wm,wm8750-pll-clock";
113 #clock-cells = <0>;
114 compatible = "wm,wm8750-pll-clock";
120 #clock-cells = <0>;
121 compatible = "wm,wm8750-pll-clock";
127 #clock-cells = <0>;
128 compatible = "via,vt8500-device-clock";
130 divisor-reg = <0x300>;
134 #clock-cells = <0>;
135 compatible = "via,vt8500-device-clock";
137 divisor-reg = <0x304>;
141 #clock-cells = <0>;
142 compatible = "via,vt8500-device-clock";
144 divisor-reg = <0x320>;
148 #clock-cells = <0>;
149 compatible = "via,vt8500-device-clock";
151 divisor-reg = <0x310>;
155 #clock-cells = <0>;
156 compatible = "via,vt8500-device-clock";
158 enable-reg = <0x254>;
159 enable-bit = <24>;
163 #clock-cells = <0>;
164 compatible = "via,vt8500-device-clock";
166 enable-reg = <0x254>;
167 enable-bit = <25>;
171 #clock-cells = <0>;
172 compatible = "via,vt8500-device-clock";
174 enable-reg = <0x254>;
175 enable-bit = <26>;
179 #clock-cells = <0>;
180 compatible = "via,vt8500-device-clock";
182 enable-reg = <0x254>;
183 enable-bit = <27>;
187 #clock-cells = <0>;
188 compatible = "via,vt8500-device-clock";
190 enable-reg = <0x254>;
191 enable-bit = <28>;
195 #clock-cells = <0>;
196 compatible = "via,vt8500-device-clock";
198 enable-reg = <0x254>;
199 enable-bit = <29>;
203 #clock-cells = <0>;
204 compatible = "via,vt8500-device-clock";
206 divisor-reg = <0x350>;
207 enable-reg = <0x250>;
208 enable-bit = <17>;
212 #clock-cells = <0>;
213 compatible = "via,vt8500-device-clock";
215 divisor-reg = <0x330>;
216 divisor-mask = <0x3f>;
217 enable-reg = <0x250>;
218 enable-bit = <0>;
222 #clock-cells = <0>;
223 compatible = "via,vt8500-device-clock";
225 divisor-reg = <0x3A0>;
226 enable-reg = <0x250>;
227 enable-bit = <8>;
231 #clock-cells = <0>;
232 compatible = "via,vt8500-device-clock";
234 divisor-reg = <0x3A4>;
235 enable-reg = <0x250>;
236 enable-bit = <9>;
242 #pwm-cells = <3>;
243 compatible = "via,vt8500-pwm";
249 compatible = "via,vt8500-timer";
255 compatible = "via,vt8500-ehci";
261 compatible = "platform-uhci";
267 compatible = "platform-uhci";
273 compatible = "via,vt8500-uart";
281 compatible = "via,vt8500-uart";
289 compatible = "via,vt8500-uart";
297 compatible = "via,vt8500-uart";
305 compatible = "via,vt8500-uart";
313 compatible = "via,vt8500-uart";
321 compatible = "via,vt8500-rtc";
327 compatible = "wm,wm8505-sdhc";
331 bus-width = <4>;
332 sdon-inverted;
336 compatible = "wm,wm8505-i2c";
340 clock-frequency = <400000>;
344 compatible = "wm,wm8505-i2c";
348 clock-frequency = <400000>;