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/linux/drivers/sh/clk/
H A Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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H A Dcpg.c5 * Copyright (C) 2010 - 2012 Paul Mundt
11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static unsigned int sh_clk_read_status(struct clk *clk) in sh_clk_read_status() argument
31 void __iomem *mapped_status = (phys_addr_t)clk->status_reg - in sh_clk_read_status()
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/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
28 #include "clk.h"
74 struct clk_core *parent; member
107 #include <trace/events/clk.h>
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H A Dclk-gate_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit tests for clk gate
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
16 pdev = platform_device_register_simple("test_gate_device", -1, NULL, 0); in clk_gate_register_test_dev()
19 ret = clk_hw_register_gate(&pdev->dev, "test_gate", NULL, 0, NULL, in clk_gate_register_test_dev()
31 struct clk_hw *parent; in clk_gate_register_test_parent_names() local
34 parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, in clk_gate_register_test_parent_names()
36 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); in clk_gate_register_test_parent_names()
41 KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); in clk_gate_register_test_parent_names()
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H A Dclk-fixed-rate_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for clk fixed rate basic type
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
11 #include <kunit/clk.h>
17 #include "clk-fixed-rate_test.h"
20 * struct clk_hw_fixed_rate_kunit_params - Parameters to pass to __clk_hw_register_fixed_rate()
21 * @dev: device registering clk
22 * @np: device_node of device registering clk
23 * @name: name of clk
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H A Dclk-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/clk-provider.h>
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
30 * parent - fixed parent. No clk_set_parent support
34 * struct clk_gpio - gpio gated clock
36 * @hw: handle between common and hardware-specific interfaces
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/linux/drivers/clk/tegra/
H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
70 * CCF assumes that neither the parent nor its rate will change during in tegra210_clk_emc_recalc_rate()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
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H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
14 #include <linux/clk/tegra.h>
27 #include "clk.h"
48 * When we change the timing to a timing with a parent that has the same
49 * clock source as the current parent, we must first change to a backup
68 struct clk *parent; member
75 struct clk *prev_parent;
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H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
16 #include <linux/reset-controller.h>
21 #include "clk.h"
31 static struct clk **clks;
35 /* Handlers for SoC-specific reset lines */
121 return -EINVAL; in tegra_clk_rst_assert()
135 return -EINVAL; in tegra_clk_rst_deassert()
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/linux/drivers/clk/ti/
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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H A Dgate.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
22 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
48 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
60 struct clk_omap_divider *parent; in omap36xx_gate_clk_enable_with_hsdiv_restore() local
68 /* Parent is the x2 node, get parent of parent for the m2 div */ in omap36xx_gate_clk_enable_with_hsdiv_restore()
70 parent = to_clk_omap_divider(parent_hw); in omap36xx_gate_clk_enable_with_hsdiv_restore()
74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
23 clocks = <&clk LOONGSON2_NODE_CLK>;
27 ref_100m: clock-ref-100m {
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H A Dloongson-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
24 clocks = <&clk LOONGSON2_NODE_CLK>;
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/linux/drivers/clk/sunxi/
H A Dclk-sun9i-cpus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
57 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
59 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
63 /* clk divider */ in sun9i_a80_cpus_clk_recalc_rate()
70 u8 parent, unsigned long parent_rate) in sun9i_a80_cpus_clk_round() argument
76 * frequencies higher than the parent frequency in sun9i_a80_cpus_clk_round()
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H A Dclk-factors.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
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/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clk/renesas.h>
31 #include <linux/reset-controller.h>
36 #include <dt-bindings/clock/renesas-cpg-mssr.h>
38 #include "rzg2l-cpg.h"
78 * struct clk_hw_data - clock hardware data
94 * struct sd_mux_hw_data - SD MUX clock hardware data
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H A Drzv2h-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on rzg2l-cpg.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 #include "rzv2h-cpg.h"
46 #define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
69 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
78 * @num_resets: Number of Module Resets in info->resets[]
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H A Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_mask: Bitmask covering the register bits to select the parent clock
33 * @parents: Array to map from valid parent clocks indices to hardware indices
51 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
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/linux/include/linux/
H A Dsh_clk.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk.h>
13 struct clk;
24 void (*init)(struct clk *clk);
26 int (*enable)(struct clk *clk);
27 void (*disable)(struct clk *clk);
28 unsigned long (*recalc)(struct clk *clk);
29 int (*set_rate)(struct clk *clk, unsigned long rate);
30 int (*set_parent)(struct clk *clk, struct clk *parent);
31 long (*round_rate)(struct clk *clk, unsigned long rate);
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/linux/drivers/clk/davinci/
H A Dda8xx-cfgchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
8 #include <linux/clk-provider.h>
9 #include <linux/clk.h>
12 #include <linux/mfd/da8xx-cfgchip.h>
15 #include <linux/platform_data/clk-da8xx-cfgchip.h>
21 /* --- Gate clocks --- */
44 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); in da8xx_cfgchip_gate_clk_enable() local
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable()
51 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); in da8xx_cfgchip_gate_clk_disable() local
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/linux/drivers/clk/keystone/
H A Dsci-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
8 #include <linux/clk-provider.h>
24 * struct sci_clk_provider - TI SCI clock provider representation
40 * struct sci_clk - TI SCI clock representation
66 * sci_clk_prepare - Prepare (enable) a TI SCI clock
73 struct sci_clk *clk = to_sci_clk(hw); in sci_clk_prepare() local
74 bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE; in sci_clk_prepare()
75 bool allow_freq_change = clk->flags & SCI_CLK_ALLOW_FREQ_CHANGE; in sci_clk_prepare()
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/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7780.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7780.c
22 static void master_clk_init(struct clk *clk) in master_clk_init() argument
24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
31 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
34 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
41 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
44 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
51 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
54 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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/linux/drivers/cpufreq/
H A Dspear-cpufreq.c2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
62 /* Get parent to sys clock */ in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
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/linux/drivers/clk/zynq/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
48 * @prate: Clock frequency of parent clock
56 fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate); in zynq_pll_determine_rate()
62 req->rate = req->best_parent_rate * fbdiv; in zynq_pll_determine_rate()
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