1*ae5bac37SInochi Amaoto// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*ae5bac37SInochi Amaoto/* 3*ae5bac37SInochi Amaoto * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> 4*ae5bac37SInochi Amaoto */ 5*ae5bac37SInochi Amaoto 6*ae5bac37SInochi Amaoto#include <dt-bindings/interrupt-controller/irq.h> 7*ae5bac37SInochi Amaoto 8*ae5bac37SInochi Amaoto#include "sg2044-cpus.dtsi" 9*ae5bac37SInochi Amaoto#include "sg2044-reset.h" 10*ae5bac37SInochi Amaoto 11*ae5bac37SInochi Amaoto/ { 12*ae5bac37SInochi Amaoto compatible = "sophgo,sg2044"; 13*ae5bac37SInochi Amaoto 14*ae5bac37SInochi Amaoto memory@80000000 { 15*ae5bac37SInochi Amaoto device_type = "memory"; 16*ae5bac37SInochi Amaoto reg = <0x00000000 0x80000000 0x00000010 0x00000000>; 17*ae5bac37SInochi Amaoto }; 18*ae5bac37SInochi Amaoto 19*ae5bac37SInochi Amaoto osc: oscillator { 20*ae5bac37SInochi Amaoto compatible = "fixed-clock"; 21*ae5bac37SInochi Amaoto clock-output-names = "osc"; 22*ae5bac37SInochi Amaoto #clock-cells = <0>; 23*ae5bac37SInochi Amaoto }; 24*ae5bac37SInochi Amaoto 25*ae5bac37SInochi Amaoto soc { 26*ae5bac37SInochi Amaoto compatible = "simple-bus"; 27*ae5bac37SInochi Amaoto #address-cells = <2>; 28*ae5bac37SInochi Amaoto #size-cells = <2>; 29*ae5bac37SInochi Amaoto ranges; 30*ae5bac37SInochi Amaoto 31*ae5bac37SInochi Amaoto uart0: serial@7030000000 { 32*ae5bac37SInochi Amaoto compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 33*ae5bac37SInochi Amaoto reg = <0x70 0x30000000 0x0 0x1000>; 34*ae5bac37SInochi Amaoto clock-frequency = <500000000>; 35*ae5bac37SInochi Amaoto interrupt-parent = <&intc>; 36*ae5bac37SInochi Amaoto interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 37*ae5bac37SInochi Amaoto reg-shift = <2>; 38*ae5bac37SInochi Amaoto reg-io-width = <4>; 39*ae5bac37SInochi Amaoto resets = <&rst RST_UART0>; 40*ae5bac37SInochi Amaoto status = "disabled"; 41*ae5bac37SInochi Amaoto }; 42*ae5bac37SInochi Amaoto 43*ae5bac37SInochi Amaoto uart1: serial@7030001000 { 44*ae5bac37SInochi Amaoto compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 45*ae5bac37SInochi Amaoto reg = <0x70 0x30001000 0x0 0x1000>; 46*ae5bac37SInochi Amaoto clock-frequency = <500000000>; 47*ae5bac37SInochi Amaoto interrupt-parent = <&intc>; 48*ae5bac37SInochi Amaoto interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; 49*ae5bac37SInochi Amaoto reg-shift = <2>; 50*ae5bac37SInochi Amaoto reg-io-width = <4>; 51*ae5bac37SInochi Amaoto resets = <&rst RST_UART1>; 52*ae5bac37SInochi Amaoto status = "disabled"; 53*ae5bac37SInochi Amaoto }; 54*ae5bac37SInochi Amaoto 55*ae5bac37SInochi Amaoto uart2: serial@7030002000 { 56*ae5bac37SInochi Amaoto compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 57*ae5bac37SInochi Amaoto reg = <0x70 0x30002000 0x0 0x1000>; 58*ae5bac37SInochi Amaoto clock-frequency = <500000000>; 59*ae5bac37SInochi Amaoto interrupt-parent = <&intc>; 60*ae5bac37SInochi Amaoto interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; 61*ae5bac37SInochi Amaoto reg-shift = <2>; 62*ae5bac37SInochi Amaoto reg-io-width = <4>; 63*ae5bac37SInochi Amaoto resets = <&rst RST_UART2>; 64*ae5bac37SInochi Amaoto status = "disabled"; 65*ae5bac37SInochi Amaoto }; 66*ae5bac37SInochi Amaoto 67*ae5bac37SInochi Amaoto uart3: serial@7030003000 { 68*ae5bac37SInochi Amaoto compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 69*ae5bac37SInochi Amaoto reg = <0x70 0x30003000 0x0 0x1000>; 70*ae5bac37SInochi Amaoto clock-frequency = <500000000>; 71*ae5bac37SInochi Amaoto interrupt-parent = <&intc>; 72*ae5bac37SInochi Amaoto interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 73*ae5bac37SInochi Amaoto reg-shift = <2>; 74*ae5bac37SInochi Amaoto reg-io-width = <4>; 75*ae5bac37SInochi Amaoto resets = <&rst RST_UART3>; 76*ae5bac37SInochi Amaoto status = "disabled"; 77*ae5bac37SInochi Amaoto }; 78*ae5bac37SInochi Amaoto 79*ae5bac37SInochi Amaoto rst: reset-controller@7050003000 { 80*ae5bac37SInochi Amaoto compatible = "sophgo,sg2044-reset", 81*ae5bac37SInochi Amaoto "sophgo,sg2042-reset"; 82*ae5bac37SInochi Amaoto reg = <0x70 0x50003000 0x0 0x1000>; 83*ae5bac37SInochi Amaoto #reset-cells = <1>; 84*ae5bac37SInochi Amaoto }; 85*ae5bac37SInochi Amaoto }; 86*ae5bac37SInochi Amaoto}; 87