1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7 8#include "sg2044-cpus.dtsi" 9#include "sg2044-reset.h" 10 11/ { 12 compatible = "sophgo,sg2044"; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x00000000 0x80000000 0x00000010 0x00000000>; 17 }; 18 19 osc: oscillator { 20 compatible = "fixed-clock"; 21 clock-output-names = "osc"; 22 #clock-cells = <0>; 23 }; 24 25 soc { 26 compatible = "simple-bus"; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 uart0: serial@7030000000 { 32 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 33 reg = <0x70 0x30000000 0x0 0x1000>; 34 clock-frequency = <500000000>; 35 interrupt-parent = <&intc>; 36 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 37 reg-shift = <2>; 38 reg-io-width = <4>; 39 resets = <&rst RST_UART0>; 40 status = "disabled"; 41 }; 42 43 uart1: serial@7030001000 { 44 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 45 reg = <0x70 0x30001000 0x0 0x1000>; 46 clock-frequency = <500000000>; 47 interrupt-parent = <&intc>; 48 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; 49 reg-shift = <2>; 50 reg-io-width = <4>; 51 resets = <&rst RST_UART1>; 52 status = "disabled"; 53 }; 54 55 uart2: serial@7030002000 { 56 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 57 reg = <0x70 0x30002000 0x0 0x1000>; 58 clock-frequency = <500000000>; 59 interrupt-parent = <&intc>; 60 interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; 61 reg-shift = <2>; 62 reg-io-width = <4>; 63 resets = <&rst RST_UART2>; 64 status = "disabled"; 65 }; 66 67 uart3: serial@7030003000 { 68 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 69 reg = <0x70 0x30003000 0x0 0x1000>; 70 clock-frequency = <500000000>; 71 interrupt-parent = <&intc>; 72 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 73 reg-shift = <2>; 74 reg-io-width = <4>; 75 resets = <&rst RST_UART3>; 76 status = "disabled"; 77 }; 78 79 rst: reset-controller@7050003000 { 80 compatible = "sophgo,sg2044-reset", 81 "sophgo,sg2042-reset"; 82 reg = <0x70 0x50003000 0x0 0x1000>; 83 #reset-cells = <1>; 84 }; 85 }; 86}; 87