130a5532aSBinbin Zhou// SPDX-License-Identifier: GPL-2.0 230a5532aSBinbin Zhou/* 330a5532aSBinbin Zhou * Copyright (C) 2023 Loongson Technology Corporation Limited 430a5532aSBinbin Zhou */ 530a5532aSBinbin Zhou 630a5532aSBinbin Zhou/dts-v1/; 730a5532aSBinbin Zhou 830a5532aSBinbin Zhou#include <dt-bindings/interrupt-controller/irq.h> 930a5532aSBinbin Zhou#include <dt-bindings/clock/loongson,ls2k-clk.h> 1030a5532aSBinbin Zhou#include <dt-bindings/gpio/gpio.h> 1130a5532aSBinbin Zhou 1230a5532aSBinbin Zhou/ { 1330a5532aSBinbin Zhou #address-cells = <2>; 1430a5532aSBinbin Zhou #size-cells = <2>; 1530a5532aSBinbin Zhou 1630a5532aSBinbin Zhou cpus { 1730a5532aSBinbin Zhou #address-cells = <1>; 1830a5532aSBinbin Zhou #size-cells = <0>; 1930a5532aSBinbin Zhou 2030a5532aSBinbin Zhou cpu0: cpu@0 { 2130a5532aSBinbin Zhou compatible = "loongson,la264"; 2230a5532aSBinbin Zhou device_type = "cpu"; 2330a5532aSBinbin Zhou reg= <0x0>; 2430a5532aSBinbin Zhou clocks = <&clk LOONGSON2_NODE_CLK>; 2530a5532aSBinbin Zhou }; 2630a5532aSBinbin Zhou 2730a5532aSBinbin Zhou cpu1: cpu@1 { 2830a5532aSBinbin Zhou compatible = "loongson,la264"; 2930a5532aSBinbin Zhou device_type = "cpu"; 3030a5532aSBinbin Zhou reg = <0x1>; 3130a5532aSBinbin Zhou clocks = <&clk LOONGSON2_NODE_CLK>; 3230a5532aSBinbin Zhou }; 3330a5532aSBinbin Zhou }; 3430a5532aSBinbin Zhou 3530a5532aSBinbin Zhou ref_100m: clock-ref-100m { 3630a5532aSBinbin Zhou compatible = "fixed-clock"; 3730a5532aSBinbin Zhou #clock-cells = <0>; 3830a5532aSBinbin Zhou clock-frequency = <100000000>; 3930a5532aSBinbin Zhou clock-output-names = "ref_100m"; 4030a5532aSBinbin Zhou }; 4130a5532aSBinbin Zhou 4230a5532aSBinbin Zhou cpuintc: interrupt-controller { 4330a5532aSBinbin Zhou compatible = "loongson,cpu-interrupt-controller"; 4430a5532aSBinbin Zhou #interrupt-cells = <1>; 4530a5532aSBinbin Zhou interrupt-controller; 4630a5532aSBinbin Zhou }; 4730a5532aSBinbin Zhou 4830a5532aSBinbin Zhou /* i2c of the dvi eeprom edid */ 4930a5532aSBinbin Zhou i2c-gpio-0 { 5030a5532aSBinbin Zhou compatible = "i2c-gpio"; 5130a5532aSBinbin Zhou scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5230a5532aSBinbin Zhou sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5330a5532aSBinbin Zhou i2c-gpio,delay-us = <5>; /* ~100 kHz */ 5430a5532aSBinbin Zhou #address-cells = <1>; 5530a5532aSBinbin Zhou #size-cells = <0>; 5630a5532aSBinbin Zhou status = "disabled"; 5730a5532aSBinbin Zhou }; 5830a5532aSBinbin Zhou 5930a5532aSBinbin Zhou /* i2c of the eeprom edid */ 6030a5532aSBinbin Zhou i2c-gpio-1 { 6130a5532aSBinbin Zhou compatible = "i2c-gpio"; 6230a5532aSBinbin Zhou scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 6330a5532aSBinbin Zhou sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 6430a5532aSBinbin Zhou i2c-gpio,delay-us = <5>; /* ~100 kHz */ 6530a5532aSBinbin Zhou #address-cells = <1>; 6630a5532aSBinbin Zhou #size-cells = <0>; 6730a5532aSBinbin Zhou status = "disabled"; 6830a5532aSBinbin Zhou }; 6930a5532aSBinbin Zhou 7030a5532aSBinbin Zhou thermal-zones { 7130a5532aSBinbin Zhou cpu-thermal { 7230a5532aSBinbin Zhou polling-delay-passive = <1000>; 7330a5532aSBinbin Zhou polling-delay = <5000>; 7430a5532aSBinbin Zhou thermal-sensors = <&tsensor 0>; 7530a5532aSBinbin Zhou 7630a5532aSBinbin Zhou trips { 7730a5532aSBinbin Zhou cpu_alert: cpu-alert { 7830a5532aSBinbin Zhou temperature = <33000>; 7930a5532aSBinbin Zhou hysteresis = <2000>; 8030a5532aSBinbin Zhou type = "active"; 8130a5532aSBinbin Zhou }; 8230a5532aSBinbin Zhou 8330a5532aSBinbin Zhou cpu_crit: cpu-crit { 8430a5532aSBinbin Zhou temperature = <85000>; 8530a5532aSBinbin Zhou hysteresis = <5000>; 8630a5532aSBinbin Zhou type = "critical"; 8730a5532aSBinbin Zhou }; 8830a5532aSBinbin Zhou }; 8930a5532aSBinbin Zhou }; 9030a5532aSBinbin Zhou }; 9130a5532aSBinbin Zhou 9230a5532aSBinbin Zhou bus@10000000 { 9330a5532aSBinbin Zhou compatible = "simple-bus"; 9430a5532aSBinbin Zhou ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>, 9530a5532aSBinbin Zhou <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>, 9630a5532aSBinbin Zhou <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>, 9730a5532aSBinbin Zhou <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>, 9830a5532aSBinbin Zhou <0xfe 0x0 0xfe 0x0 0x0 0x40000000>; 9930a5532aSBinbin Zhou #address-cells = <2>; 10030a5532aSBinbin Zhou #size-cells = <2>; 10130a5532aSBinbin Zhou dma-coherent; 10230a5532aSBinbin Zhou 103ec2bbc57SHuacai Chen isa@18000000 { 104ec2bbc57SHuacai Chen compatible = "isa"; 105ec2bbc57SHuacai Chen #size-cells = <1>; 106ec2bbc57SHuacai Chen #address-cells = <2>; 107ec2bbc57SHuacai Chen ranges = <1 0x0 0x0 0x18000000 0x4000>; 108ec2bbc57SHuacai Chen }; 109ec2bbc57SHuacai Chen 11030a5532aSBinbin Zhou liointc0: interrupt-controller@1fe01400 { 11130a5532aSBinbin Zhou compatible = "loongson,liointc-2.0"; 11230a5532aSBinbin Zhou reg = <0x0 0x1fe01400 0x0 0x40>, 11330a5532aSBinbin Zhou <0x0 0x1fe01040 0x0 0x8>, 11430a5532aSBinbin Zhou <0x0 0x1fe01140 0x0 0x8>; 11530a5532aSBinbin Zhou reg-names = "main", "isr0", "isr1"; 11630a5532aSBinbin Zhou interrupt-controller; 11730a5532aSBinbin Zhou #interrupt-cells = <2>; 11830a5532aSBinbin Zhou interrupt-parent = <&cpuintc>; 11930a5532aSBinbin Zhou interrupts = <2>; 12030a5532aSBinbin Zhou interrupt-names = "int0"; 12130a5532aSBinbin Zhou loongson,parent_int_map = <0xffffffff>, /* int0 */ 12230a5532aSBinbin Zhou <0x00000000>, /* int1 */ 12330a5532aSBinbin Zhou <0x00000000>, /* int2 */ 12430a5532aSBinbin Zhou <0x00000000>; /* int3 */ 12530a5532aSBinbin Zhou }; 12630a5532aSBinbin Zhou 12730a5532aSBinbin Zhou liointc1: interrupt-controller@1fe01440 { 12830a5532aSBinbin Zhou compatible = "loongson,liointc-2.0"; 12930a5532aSBinbin Zhou reg = <0x0 0x1fe01440 0x0 0x40>, 13030a5532aSBinbin Zhou <0x0 0x1fe01048 0x0 0x8>, 13130a5532aSBinbin Zhou <0x0 0x1fe01148 0x0 0x8>; 13230a5532aSBinbin Zhou reg-names = "main", "isr0", "isr1"; 13330a5532aSBinbin Zhou interrupt-controller; 13430a5532aSBinbin Zhou #interrupt-cells = <2>; 13530a5532aSBinbin Zhou interrupt-parent = <&cpuintc>; 13630a5532aSBinbin Zhou interrupts = <3>; 13730a5532aSBinbin Zhou interrupt-names = "int1"; 13830a5532aSBinbin Zhou loongson,parent_int_map = <0x00000000>, /* int0 */ 13930a5532aSBinbin Zhou <0xffffffff>, /* int1 */ 14030a5532aSBinbin Zhou <0x00000000>, /* int2 */ 14130a5532aSBinbin Zhou <0x00000000>; /* int3 */ 14230a5532aSBinbin Zhou }; 14330a5532aSBinbin Zhou 14430a5532aSBinbin Zhou chipid@1fe00000 { 14530a5532aSBinbin Zhou compatible = "loongson,ls2k-chipid"; 14630a5532aSBinbin Zhou reg = <0x0 0x1fe00000 0x0 0x30>; 14730a5532aSBinbin Zhou little-endian; 14830a5532aSBinbin Zhou }; 14930a5532aSBinbin Zhou 15030a5532aSBinbin Zhou pctrl: pinctrl@1fe00420 { 15130a5532aSBinbin Zhou compatible = "loongson,ls2k-pinctrl"; 15230a5532aSBinbin Zhou reg = <0x0 0x1fe00420 0x0 0x18>; 15330a5532aSBinbin Zhou status = "disabled"; 15430a5532aSBinbin Zhou }; 15530a5532aSBinbin Zhou 15630a5532aSBinbin Zhou clk: clock-controller@1fe00480 { 15730a5532aSBinbin Zhou compatible = "loongson,ls2k-clk"; 15830a5532aSBinbin Zhou reg = <0x0 0x1fe00480 0x0 0x58>; 15930a5532aSBinbin Zhou #clock-cells = <1>; 16030a5532aSBinbin Zhou clocks = <&ref_100m>; 16130a5532aSBinbin Zhou clock-names = "ref_100m"; 16230a5532aSBinbin Zhou }; 16330a5532aSBinbin Zhou 16430a5532aSBinbin Zhou gpio0: gpio@1fe00500 { 16530a5532aSBinbin Zhou compatible = "loongson,ls2k-gpio"; 16630a5532aSBinbin Zhou reg = <0x0 0x1fe00500 0x0 0x38>; 16730a5532aSBinbin Zhou ngpios = <64>; 16830a5532aSBinbin Zhou #gpio-cells = <2>; 16930a5532aSBinbin Zhou gpio-controller; 17030a5532aSBinbin Zhou gpio-ranges = <&pctrl 0x0 0x0 15>, 17130a5532aSBinbin Zhou <&pctrl 16 16 15>, 17230a5532aSBinbin Zhou <&pctrl 32 32 10>, 17330a5532aSBinbin Zhou <&pctrl 44 44 20>; 17430a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 17530a5532aSBinbin Zhou interrupts = <28 IRQ_TYPE_LEVEL_HIGH>, 17630a5532aSBinbin Zhou <29 IRQ_TYPE_LEVEL_HIGH>, 17730a5532aSBinbin Zhou <30 IRQ_TYPE_LEVEL_HIGH>, 17830a5532aSBinbin Zhou <30 IRQ_TYPE_LEVEL_HIGH>, 17930a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18030a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18130a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18230a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18330a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18430a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18530a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18630a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18730a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18830a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 18930a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19030a5532aSBinbin Zhou <>, 19130a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19230a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19330a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19430a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19530a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19630a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19730a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19830a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 19930a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20030a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20130a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20230a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20330a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20430a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20530a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20630a5532aSBinbin Zhou <26 IRQ_TYPE_LEVEL_HIGH>, 20730a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 20830a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 20930a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 21030a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 21130a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 21230a5532aSBinbin Zhou <>, 21330a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 21430a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 21530a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 21630a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 21730a5532aSBinbin Zhou <>, 21830a5532aSBinbin Zhou <>, 21930a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22030a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22130a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22230a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22330a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22430a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22530a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22630a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22730a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22830a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 22930a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23030a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23130a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23230a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23330a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23430a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23530a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23630a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23730a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>, 23830a5532aSBinbin Zhou <27 IRQ_TYPE_LEVEL_HIGH>; 23930a5532aSBinbin Zhou }; 24030a5532aSBinbin Zhou 24130a5532aSBinbin Zhou tsensor: thermal-sensor@1fe01500 { 24230a5532aSBinbin Zhou compatible = "loongson,ls2k1000-thermal"; 24330a5532aSBinbin Zhou reg = <0x0 0x1fe01500 0x0 0x30>; 24430a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 24530a5532aSBinbin Zhou interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 24630a5532aSBinbin Zhou #thermal-sensor-cells = <1>; 24730a5532aSBinbin Zhou }; 24830a5532aSBinbin Zhou 24930a5532aSBinbin Zhou dma-controller@1fe00c00 { 25030a5532aSBinbin Zhou compatible = "loongson,ls2k1000-apbdma"; 25130a5532aSBinbin Zhou reg = <0x0 0x1fe00c00 0x0 0x8>; 25230a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 25330a5532aSBinbin Zhou interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 25430a5532aSBinbin Zhou clocks = <&clk LOONGSON2_APB_CLK>; 25530a5532aSBinbin Zhou #dma-cells = <1>; 25630a5532aSBinbin Zhou status = "disabled"; 25730a5532aSBinbin Zhou }; 25830a5532aSBinbin Zhou 25930a5532aSBinbin Zhou dma-controller@1fe00c10 { 26030a5532aSBinbin Zhou compatible = "loongson,ls2k1000-apbdma"; 26130a5532aSBinbin Zhou reg = <0x0 0x1fe00c10 0x0 0x8>; 26230a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 26330a5532aSBinbin Zhou interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 26430a5532aSBinbin Zhou clocks = <&clk LOONGSON2_APB_CLK>; 26530a5532aSBinbin Zhou #dma-cells = <1>; 26630a5532aSBinbin Zhou status = "disabled"; 26730a5532aSBinbin Zhou }; 26830a5532aSBinbin Zhou 269*b7915af6SBinbin Zhou apbdma2: dma-controller@1fe00c20 { 27030a5532aSBinbin Zhou compatible = "loongson,ls2k1000-apbdma"; 27130a5532aSBinbin Zhou reg = <0x0 0x1fe00c20 0x0 0x8>; 27230a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 27330a5532aSBinbin Zhou interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 27430a5532aSBinbin Zhou clocks = <&clk LOONGSON2_APB_CLK>; 27530a5532aSBinbin Zhou #dma-cells = <1>; 27630a5532aSBinbin Zhou status = "disabled"; 27730a5532aSBinbin Zhou }; 27830a5532aSBinbin Zhou 279*b7915af6SBinbin Zhou apbdma3: dma-controller@1fe00c30 { 28030a5532aSBinbin Zhou compatible = "loongson,ls2k1000-apbdma"; 28130a5532aSBinbin Zhou reg = <0x0 0x1fe00c30 0x0 0x8>; 28230a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 28330a5532aSBinbin Zhou interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; 28430a5532aSBinbin Zhou clocks = <&clk LOONGSON2_APB_CLK>; 28530a5532aSBinbin Zhou #dma-cells = <1>; 28630a5532aSBinbin Zhou status = "disabled"; 28730a5532aSBinbin Zhou }; 28830a5532aSBinbin Zhou 28930a5532aSBinbin Zhou dma-controller@1fe00c40 { 29030a5532aSBinbin Zhou compatible = "loongson,ls2k1000-apbdma"; 29130a5532aSBinbin Zhou reg = <0x0 0x1fe00c40 0x0 0x8>; 29230a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 29330a5532aSBinbin Zhou interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 29430a5532aSBinbin Zhou clocks = <&clk LOONGSON2_APB_CLK>; 29530a5532aSBinbin Zhou #dma-cells = <1>; 29630a5532aSBinbin Zhou status = "disabled"; 29730a5532aSBinbin Zhou }; 29830a5532aSBinbin Zhou 29930a5532aSBinbin Zhou uart0: serial@1fe20000 { 30030a5532aSBinbin Zhou compatible = "ns16550a"; 30130a5532aSBinbin Zhou reg = <0x0 0x1fe20000 0x0 0x10>; 30230a5532aSBinbin Zhou clock-frequency = <125000000>; 30330a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 30430a5532aSBinbin Zhou interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>; 30530a5532aSBinbin Zhou no-loopback-test; 30630a5532aSBinbin Zhou status = "disabled"; 30730a5532aSBinbin Zhou }; 30830a5532aSBinbin Zhou 30930a5532aSBinbin Zhou i2c2: i2c@1fe21000 { 31030a5532aSBinbin Zhou compatible = "loongson,ls2k-i2c"; 31130a5532aSBinbin Zhou reg = <0x0 0x1fe21000 0x0 0x8>; 31230a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 31330a5532aSBinbin Zhou interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 31430a5532aSBinbin Zhou status = "disabled"; 31530a5532aSBinbin Zhou }; 31630a5532aSBinbin Zhou 31730a5532aSBinbin Zhou i2c3: i2c@1fe21800 { 31830a5532aSBinbin Zhou compatible = "loongson,ls2k-i2c"; 31930a5532aSBinbin Zhou reg = <0x0 0x1fe21800 0x0 0x8>; 32030a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 32130a5532aSBinbin Zhou interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 32230a5532aSBinbin Zhou status = "disabled"; 32330a5532aSBinbin Zhou }; 32430a5532aSBinbin Zhou 32530a5532aSBinbin Zhou pmc: power-management@1fe27000 { 32630a5532aSBinbin Zhou compatible = "loongson,ls2k1000-pmc", "loongson,ls2k0500-pmc", "syscon"; 32730a5532aSBinbin Zhou reg = <0x0 0x1fe27000 0x0 0x58>; 32830a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 32930a5532aSBinbin Zhou interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 33030a5532aSBinbin Zhou loongson,suspend-address = <0x0 0x1c000500>; 33130a5532aSBinbin Zhou 33230a5532aSBinbin Zhou syscon-reboot { 33330a5532aSBinbin Zhou compatible = "syscon-reboot"; 33430a5532aSBinbin Zhou offset = <0x30>; 33530a5532aSBinbin Zhou mask = <0x1>; 33630a5532aSBinbin Zhou }; 33730a5532aSBinbin Zhou 33830a5532aSBinbin Zhou syscon-poweroff { 33930a5532aSBinbin Zhou compatible = "syscon-poweroff"; 34030a5532aSBinbin Zhou regmap = <&pmc>; 34130a5532aSBinbin Zhou offset = <0x14>; 34230a5532aSBinbin Zhou mask = <0x3c00>; 34330a5532aSBinbin Zhou value = <0x3c00>; 34430a5532aSBinbin Zhou }; 34530a5532aSBinbin Zhou }; 34630a5532aSBinbin Zhou 34730a5532aSBinbin Zhou rtc0: rtc@1fe27800 { 34830a5532aSBinbin Zhou compatible = "loongson,ls2k1000-rtc"; 34930a5532aSBinbin Zhou reg = <0x0 0x1fe27800 0x0 0x100>; 35030a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 35130a5532aSBinbin Zhou interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 35230a5532aSBinbin Zhou status = "disabled"; 35330a5532aSBinbin Zhou }; 35430a5532aSBinbin Zhou 355*b7915af6SBinbin Zhou i2s: i2s@1fe2d000 { 356*b7915af6SBinbin Zhou compatible = "loongson,ls2k1000-i2s"; 357*b7915af6SBinbin Zhou reg = <0 0x1fe2d000 0 0x14>, 358*b7915af6SBinbin Zhou <0 0x1fe00438 0 0x8>; 359*b7915af6SBinbin Zhou interrupt-parent = <&liointc0>; 360*b7915af6SBinbin Zhou interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 361*b7915af6SBinbin Zhou clocks = <&clk LOONGSON2_APB_CLK>; 362*b7915af6SBinbin Zhou dmas = <&apbdma2 0>, <&apbdma3 0>; 363*b7915af6SBinbin Zhou dma-names = "tx", "rx"; 364*b7915af6SBinbin Zhou #sound-dai-cells = <0>; 365*b7915af6SBinbin Zhou status = "disabled"; 366*b7915af6SBinbin Zhou }; 367*b7915af6SBinbin Zhou 36830a5532aSBinbin Zhou spi0: spi@1fff0220 { 36930a5532aSBinbin Zhou compatible = "loongson,ls2k1000-spi"; 37030a5532aSBinbin Zhou reg = <0x0 0x1fff0220 0x0 0x10>; 37130a5532aSBinbin Zhou clocks = <&clk LOONGSON2_BOOT_CLK>; 37230a5532aSBinbin Zhou status = "disabled"; 37330a5532aSBinbin Zhou }; 37430a5532aSBinbin Zhou 37530a5532aSBinbin Zhou pcie@1a000000 { 37630a5532aSBinbin Zhou compatible = "loongson,ls2k-pci"; 37730a5532aSBinbin Zhou reg = <0x0 0x1a000000 0x0 0x02000000>, 37830a5532aSBinbin Zhou <0xfe 0x0 0x0 0x20000000>; 37930a5532aSBinbin Zhou #address-cells = <3>; 38030a5532aSBinbin Zhou #size-cells = <2>; 38130a5532aSBinbin Zhou device_type = "pci"; 38230a5532aSBinbin Zhou bus-range = <0x0 0xff>; 38330a5532aSBinbin Zhou ranges = <0x01000000 0x0 0x00008000 0x0 0x18008000 0x0 0x00008000>, 38430a5532aSBinbin Zhou <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; 38530a5532aSBinbin Zhou 38630a5532aSBinbin Zhou gmac0: ethernet@3,0 { 38730a5532aSBinbin Zhou reg = <0x1800 0x0 0x0 0x0 0x0>; 38830a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 38930a5532aSBinbin Zhou interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 39030a5532aSBinbin Zhou <13 IRQ_TYPE_LEVEL_HIGH>; 39130a5532aSBinbin Zhou interrupt-names = "macirq", "eth_lpi"; 39230a5532aSBinbin Zhou status = "disabled"; 39330a5532aSBinbin Zhou }; 39430a5532aSBinbin Zhou 39530a5532aSBinbin Zhou gmac1: ethernet@3,1 { 39630a5532aSBinbin Zhou reg = <0x1900 0x0 0x0 0x0 0x0>; 39730a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 39830a5532aSBinbin Zhou interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 39930a5532aSBinbin Zhou <15 IRQ_TYPE_LEVEL_HIGH>; 40030a5532aSBinbin Zhou interrupt-names = "macirq", "eth_lpi"; 40130a5532aSBinbin Zhou status = "disabled"; 40230a5532aSBinbin Zhou }; 40330a5532aSBinbin Zhou 40430a5532aSBinbin Zhou ehci0: usb@4,1 { 40530a5532aSBinbin Zhou reg = <0x2100 0x0 0x0 0x0 0x0>; 40630a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 40730a5532aSBinbin Zhou interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 40830a5532aSBinbin Zhou status = "disabled"; 40930a5532aSBinbin Zhou }; 41030a5532aSBinbin Zhou 41130a5532aSBinbin Zhou ohci0: usb@4,2 { 41230a5532aSBinbin Zhou reg = <0x2200 0x0 0x0 0x0 0x0>; 41330a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 41430a5532aSBinbin Zhou interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 41530a5532aSBinbin Zhou status = "disabled"; 41630a5532aSBinbin Zhou }; 41730a5532aSBinbin Zhou 41830a5532aSBinbin Zhou display@6,0 { 41930a5532aSBinbin Zhou reg = <0x3000 0x0 0x0 0x0 0x0>; 42030a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 42130a5532aSBinbin Zhou interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 42230a5532aSBinbin Zhou status = "disabled"; 42330a5532aSBinbin Zhou }; 42430a5532aSBinbin Zhou 42530a5532aSBinbin Zhou hda@7,0 { 42630a5532aSBinbin Zhou reg = <0x3800 0x0 0x0 0x0 0x0>; 42730a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 42830a5532aSBinbin Zhou interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 42930a5532aSBinbin Zhou status = "disabled"; 43030a5532aSBinbin Zhou }; 43130a5532aSBinbin Zhou 43230a5532aSBinbin Zhou sata: sata@8,0 { 43330a5532aSBinbin Zhou reg = <0x4000 0x0 0x0 0x0 0x0>; 43430a5532aSBinbin Zhou interrupt-parent = <&liointc0>; 43530a5532aSBinbin Zhou interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 43630a5532aSBinbin Zhou status = "disabled"; 43730a5532aSBinbin Zhou }; 43830a5532aSBinbin Zhou 43930a5532aSBinbin Zhou pcie@9,0 { 44030a5532aSBinbin Zhou reg = <0x4800 0x0 0x0 0x0 0x0>; 44130a5532aSBinbin Zhou #address-cells = <3>; 44230a5532aSBinbin Zhou #size-cells = <2>; 44330a5532aSBinbin Zhou device_type = "pci"; 44430a5532aSBinbin Zhou #interrupt-cells = <1>; 44530a5532aSBinbin Zhou interrupt-map-mask = <0x0 0x0 0x0 0x0>; 44630a5532aSBinbin Zhou interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 0x0 IRQ_TYPE_LEVEL_HIGH>; 44730a5532aSBinbin Zhou ranges; 44830a5532aSBinbin Zhou }; 44930a5532aSBinbin Zhou 45030a5532aSBinbin Zhou pcie@a,0 { 45130a5532aSBinbin Zhou reg = <0x5000 0x0 0x0 0x0 0x0>; 45230a5532aSBinbin Zhou #address-cells = <3>; 45330a5532aSBinbin Zhou #size-cells = <2>; 45430a5532aSBinbin Zhou device_type = "pci"; 45530a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 45630a5532aSBinbin Zhou #interrupt-cells = <1>; 45730a5532aSBinbin Zhou interrupt-map-mask = <0x0 0x0 0x0 0x0>; 45830a5532aSBinbin Zhou interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>; 45930a5532aSBinbin Zhou ranges; 46030a5532aSBinbin Zhou }; 46130a5532aSBinbin Zhou 46230a5532aSBinbin Zhou pcie@b,0 { 46330a5532aSBinbin Zhou reg = <0x5800 0x0 0x0 0x0 0x0>; 46430a5532aSBinbin Zhou #address-cells = <3>; 46530a5532aSBinbin Zhou #size-cells = <2>; 46630a5532aSBinbin Zhou device_type = "pci"; 46730a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 46830a5532aSBinbin Zhou #interrupt-cells = <1>; 46930a5532aSBinbin Zhou interrupt-map-mask = <0x0 0x0 0x0 0x0>; 47030a5532aSBinbin Zhou interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>; 47130a5532aSBinbin Zhou ranges; 47230a5532aSBinbin Zhou }; 47330a5532aSBinbin Zhou 47430a5532aSBinbin Zhou pcie@c,0 { 47530a5532aSBinbin Zhou reg = <0x6000 0x0 0x0 0x0 0x0>; 47630a5532aSBinbin Zhou #address-cells = <3>; 47730a5532aSBinbin Zhou #size-cells = <2>; 47830a5532aSBinbin Zhou device_type = "pci"; 47930a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 48030a5532aSBinbin Zhou #interrupt-cells = <1>; 48130a5532aSBinbin Zhou interrupt-map-mask = <0x0 0x0 0x0 0x0>; 48230a5532aSBinbin Zhou interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>; 48330a5532aSBinbin Zhou ranges; 48430a5532aSBinbin Zhou }; 48530a5532aSBinbin Zhou 48630a5532aSBinbin Zhou pcie@d,0 { 48730a5532aSBinbin Zhou reg = <0x6800 0x0 0x0 0x0 0x0>; 48830a5532aSBinbin Zhou #address-cells = <3>; 48930a5532aSBinbin Zhou #size-cells = <2>; 49030a5532aSBinbin Zhou device_type = "pci"; 49130a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 49230a5532aSBinbin Zhou #interrupt-cells = <1>; 49330a5532aSBinbin Zhou interrupt-map-mask = <0x0 0x0 0x0 0x0>; 49430a5532aSBinbin Zhou interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>; 49530a5532aSBinbin Zhou ranges; 49630a5532aSBinbin Zhou }; 49730a5532aSBinbin Zhou 49830a5532aSBinbin Zhou pcie@e,0 { 49930a5532aSBinbin Zhou reg = <0x7000 0x0 0x0 0x0 0x0>; 50030a5532aSBinbin Zhou #address-cells = <3>; 50130a5532aSBinbin Zhou #size-cells = <2>; 50230a5532aSBinbin Zhou device_type = "pci"; 50330a5532aSBinbin Zhou interrupt-parent = <&liointc1>; 50430a5532aSBinbin Zhou #interrupt-cells = <1>; 50530a5532aSBinbin Zhou interrupt-map-mask = <0x0 0x0 0x0 0x0>; 50630a5532aSBinbin Zhou interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>; 50730a5532aSBinbin Zhou ranges; 50830a5532aSBinbin Zhou }; 50930a5532aSBinbin Zhou }; 51030a5532aSBinbin Zhou }; 51130a5532aSBinbin Zhou}; 512