1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Loongson Technology Corporation Limited 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/clock/loongson,ls2k-clk.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "loongson,la264"; 22 device_type = "cpu"; 23 reg= <0x0>; 24 clocks = <&clk LOONGSON2_NODE_CLK>; 25 }; 26 27 cpu1: cpu@1 { 28 compatible = "loongson,la264"; 29 device_type = "cpu"; 30 reg = <0x1>; 31 clocks = <&clk LOONGSON2_NODE_CLK>; 32 }; 33 }; 34 35 ref_100m: clock-ref-100m { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <100000000>; 39 clock-output-names = "ref_100m"; 40 }; 41 42 cpuintc: interrupt-controller { 43 compatible = "loongson,cpu-interrupt-controller"; 44 #interrupt-cells = <1>; 45 interrupt-controller; 46 }; 47 48 /* i2c of the dvi eeprom edid */ 49 i2c-gpio-0 { 50 compatible = "i2c-gpio"; 51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 52 sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 53 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 54 #address-cells = <1>; 55 #size-cells = <0>; 56 status = "disabled"; 57 }; 58 59 /* i2c of the eeprom edid */ 60 i2c-gpio-1 { 61 compatible = "i2c-gpio"; 62 scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 63 sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 64 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 65 #address-cells = <1>; 66 #size-cells = <0>; 67 status = "disabled"; 68 }; 69 70 thermal-zones { 71 cpu-thermal { 72 polling-delay-passive = <1000>; 73 polling-delay = <5000>; 74 thermal-sensors = <&tsensor 0>; 75 76 trips { 77 cpu_alert: cpu-alert { 78 temperature = <33000>; 79 hysteresis = <2000>; 80 type = "active"; 81 }; 82 83 cpu_crit: cpu-crit { 84 temperature = <85000>; 85 hysteresis = <5000>; 86 type = "critical"; 87 }; 88 }; 89 }; 90 }; 91 92 bus@10000000 { 93 compatible = "simple-bus"; 94 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>, 95 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>, 96 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>, 97 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>, 98 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>; 99 #address-cells = <2>; 100 #size-cells = <2>; 101 dma-coherent; 102 103 isa@18000000 { 104 compatible = "isa"; 105 #size-cells = <1>; 106 #address-cells = <2>; 107 ranges = <1 0x0 0x0 0x18000000 0x4000>; 108 }; 109 110 liointc0: interrupt-controller@1fe01400 { 111 compatible = "loongson,liointc-2.0"; 112 reg = <0x0 0x1fe01400 0x0 0x40>, 113 <0x0 0x1fe01040 0x0 0x8>, 114 <0x0 0x1fe01140 0x0 0x8>; 115 reg-names = "main", "isr0", "isr1"; 116 interrupt-controller; 117 #interrupt-cells = <2>; 118 interrupt-parent = <&cpuintc>; 119 interrupts = <2>; 120 interrupt-names = "int0"; 121 loongson,parent_int_map = <0xffffffff>, /* int0 */ 122 <0x00000000>, /* int1 */ 123 <0x00000000>, /* int2 */ 124 <0x00000000>; /* int3 */ 125 }; 126 127 liointc1: interrupt-controller@1fe01440 { 128 compatible = "loongson,liointc-2.0"; 129 reg = <0x0 0x1fe01440 0x0 0x40>, 130 <0x0 0x1fe01048 0x0 0x8>, 131 <0x0 0x1fe01148 0x0 0x8>; 132 reg-names = "main", "isr0", "isr1"; 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 interrupt-parent = <&cpuintc>; 136 interrupts = <3>; 137 interrupt-names = "int1"; 138 loongson,parent_int_map = <0x00000000>, /* int0 */ 139 <0xffffffff>, /* int1 */ 140 <0x00000000>, /* int2 */ 141 <0x00000000>; /* int3 */ 142 }; 143 144 chipid@1fe00000 { 145 compatible = "loongson,ls2k-chipid"; 146 reg = <0x0 0x1fe00000 0x0 0x30>; 147 little-endian; 148 }; 149 150 pctrl: pinctrl@1fe00420 { 151 compatible = "loongson,ls2k-pinctrl"; 152 reg = <0x0 0x1fe00420 0x0 0x18>; 153 status = "disabled"; 154 }; 155 156 clk: clock-controller@1fe00480 { 157 compatible = "loongson,ls2k-clk"; 158 reg = <0x0 0x1fe00480 0x0 0x58>; 159 #clock-cells = <1>; 160 clocks = <&ref_100m>; 161 clock-names = "ref_100m"; 162 }; 163 164 gpio0: gpio@1fe00500 { 165 compatible = "loongson,ls2k-gpio"; 166 reg = <0x0 0x1fe00500 0x0 0x38>; 167 ngpios = <64>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pctrl 0x0 0x0 15>, 171 <&pctrl 16 16 15>, 172 <&pctrl 32 32 10>, 173 <&pctrl 44 44 20>; 174 interrupt-parent = <&liointc1>; 175 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>, 176 <29 IRQ_TYPE_LEVEL_HIGH>, 177 <30 IRQ_TYPE_LEVEL_HIGH>, 178 <30 IRQ_TYPE_LEVEL_HIGH>, 179 <26 IRQ_TYPE_LEVEL_HIGH>, 180 <26 IRQ_TYPE_LEVEL_HIGH>, 181 <26 IRQ_TYPE_LEVEL_HIGH>, 182 <26 IRQ_TYPE_LEVEL_HIGH>, 183 <26 IRQ_TYPE_LEVEL_HIGH>, 184 <26 IRQ_TYPE_LEVEL_HIGH>, 185 <26 IRQ_TYPE_LEVEL_HIGH>, 186 <26 IRQ_TYPE_LEVEL_HIGH>, 187 <26 IRQ_TYPE_LEVEL_HIGH>, 188 <26 IRQ_TYPE_LEVEL_HIGH>, 189 <26 IRQ_TYPE_LEVEL_HIGH>, 190 <>, 191 <26 IRQ_TYPE_LEVEL_HIGH>, 192 <26 IRQ_TYPE_LEVEL_HIGH>, 193 <26 IRQ_TYPE_LEVEL_HIGH>, 194 <26 IRQ_TYPE_LEVEL_HIGH>, 195 <26 IRQ_TYPE_LEVEL_HIGH>, 196 <26 IRQ_TYPE_LEVEL_HIGH>, 197 <26 IRQ_TYPE_LEVEL_HIGH>, 198 <26 IRQ_TYPE_LEVEL_HIGH>, 199 <26 IRQ_TYPE_LEVEL_HIGH>, 200 <26 IRQ_TYPE_LEVEL_HIGH>, 201 <26 IRQ_TYPE_LEVEL_HIGH>, 202 <26 IRQ_TYPE_LEVEL_HIGH>, 203 <26 IRQ_TYPE_LEVEL_HIGH>, 204 <26 IRQ_TYPE_LEVEL_HIGH>, 205 <26 IRQ_TYPE_LEVEL_HIGH>, 206 <26 IRQ_TYPE_LEVEL_HIGH>, 207 <27 IRQ_TYPE_LEVEL_HIGH>, 208 <27 IRQ_TYPE_LEVEL_HIGH>, 209 <27 IRQ_TYPE_LEVEL_HIGH>, 210 <27 IRQ_TYPE_LEVEL_HIGH>, 211 <27 IRQ_TYPE_LEVEL_HIGH>, 212 <>, 213 <27 IRQ_TYPE_LEVEL_HIGH>, 214 <27 IRQ_TYPE_LEVEL_HIGH>, 215 <27 IRQ_TYPE_LEVEL_HIGH>, 216 <27 IRQ_TYPE_LEVEL_HIGH>, 217 <>, 218 <>, 219 <27 IRQ_TYPE_LEVEL_HIGH>, 220 <27 IRQ_TYPE_LEVEL_HIGH>, 221 <27 IRQ_TYPE_LEVEL_HIGH>, 222 <27 IRQ_TYPE_LEVEL_HIGH>, 223 <27 IRQ_TYPE_LEVEL_HIGH>, 224 <27 IRQ_TYPE_LEVEL_HIGH>, 225 <27 IRQ_TYPE_LEVEL_HIGH>, 226 <27 IRQ_TYPE_LEVEL_HIGH>, 227 <27 IRQ_TYPE_LEVEL_HIGH>, 228 <27 IRQ_TYPE_LEVEL_HIGH>, 229 <27 IRQ_TYPE_LEVEL_HIGH>, 230 <27 IRQ_TYPE_LEVEL_HIGH>, 231 <27 IRQ_TYPE_LEVEL_HIGH>, 232 <27 IRQ_TYPE_LEVEL_HIGH>, 233 <27 IRQ_TYPE_LEVEL_HIGH>, 234 <27 IRQ_TYPE_LEVEL_HIGH>, 235 <27 IRQ_TYPE_LEVEL_HIGH>, 236 <27 IRQ_TYPE_LEVEL_HIGH>, 237 <27 IRQ_TYPE_LEVEL_HIGH>, 238 <27 IRQ_TYPE_LEVEL_HIGH>; 239 }; 240 241 tsensor: thermal-sensor@1fe01500 { 242 compatible = "loongson,ls2k1000-thermal"; 243 reg = <0x0 0x1fe01500 0x0 0x30>; 244 interrupt-parent = <&liointc0>; 245 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 246 #thermal-sensor-cells = <1>; 247 }; 248 249 dma-controller@1fe00c00 { 250 compatible = "loongson,ls2k1000-apbdma"; 251 reg = <0x0 0x1fe00c00 0x0 0x8>; 252 interrupt-parent = <&liointc1>; 253 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&clk LOONGSON2_APB_CLK>; 255 #dma-cells = <1>; 256 status = "disabled"; 257 }; 258 259 dma-controller@1fe00c10 { 260 compatible = "loongson,ls2k1000-apbdma"; 261 reg = <0x0 0x1fe00c10 0x0 0x8>; 262 interrupt-parent = <&liointc1>; 263 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&clk LOONGSON2_APB_CLK>; 265 #dma-cells = <1>; 266 status = "disabled"; 267 }; 268 269 dma-controller@1fe00c20 { 270 compatible = "loongson,ls2k1000-apbdma"; 271 reg = <0x0 0x1fe00c20 0x0 0x8>; 272 interrupt-parent = <&liointc1>; 273 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&clk LOONGSON2_APB_CLK>; 275 #dma-cells = <1>; 276 status = "disabled"; 277 }; 278 279 dma-controller@1fe00c30 { 280 compatible = "loongson,ls2k1000-apbdma"; 281 reg = <0x0 0x1fe00c30 0x0 0x8>; 282 interrupt-parent = <&liointc1>; 283 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&clk LOONGSON2_APB_CLK>; 285 #dma-cells = <1>; 286 status = "disabled"; 287 }; 288 289 dma-controller@1fe00c40 { 290 compatible = "loongson,ls2k1000-apbdma"; 291 reg = <0x0 0x1fe00c40 0x0 0x8>; 292 interrupt-parent = <&liointc1>; 293 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clk LOONGSON2_APB_CLK>; 295 #dma-cells = <1>; 296 status = "disabled"; 297 }; 298 299 uart0: serial@1fe20000 { 300 compatible = "ns16550a"; 301 reg = <0x0 0x1fe20000 0x0 0x10>; 302 clock-frequency = <125000000>; 303 interrupt-parent = <&liointc0>; 304 interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>; 305 no-loopback-test; 306 status = "disabled"; 307 }; 308 309 i2c2: i2c@1fe21000 { 310 compatible = "loongson,ls2k-i2c"; 311 reg = <0x0 0x1fe21000 0x0 0x8>; 312 interrupt-parent = <&liointc0>; 313 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 314 status = "disabled"; 315 }; 316 317 i2c3: i2c@1fe21800 { 318 compatible = "loongson,ls2k-i2c"; 319 reg = <0x0 0x1fe21800 0x0 0x8>; 320 interrupt-parent = <&liointc0>; 321 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 322 status = "disabled"; 323 }; 324 325 pmc: power-management@1fe27000 { 326 compatible = "loongson,ls2k1000-pmc", "loongson,ls2k0500-pmc", "syscon"; 327 reg = <0x0 0x1fe27000 0x0 0x58>; 328 interrupt-parent = <&liointc1>; 329 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 330 loongson,suspend-address = <0x0 0x1c000500>; 331 332 syscon-reboot { 333 compatible = "syscon-reboot"; 334 offset = <0x30>; 335 mask = <0x1>; 336 }; 337 338 syscon-poweroff { 339 compatible = "syscon-poweroff"; 340 regmap = <&pmc>; 341 offset = <0x14>; 342 mask = <0x3c00>; 343 value = <0x3c00>; 344 }; 345 }; 346 347 rtc0: rtc@1fe27800 { 348 compatible = "loongson,ls2k1000-rtc"; 349 reg = <0x0 0x1fe27800 0x0 0x100>; 350 interrupt-parent = <&liointc1>; 351 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 352 status = "disabled"; 353 }; 354 355 spi0: spi@1fff0220 { 356 compatible = "loongson,ls2k1000-spi"; 357 reg = <0x0 0x1fff0220 0x0 0x10>; 358 clocks = <&clk LOONGSON2_BOOT_CLK>; 359 status = "disabled"; 360 }; 361 362 pcie@1a000000 { 363 compatible = "loongson,ls2k-pci"; 364 reg = <0x0 0x1a000000 0x0 0x02000000>, 365 <0xfe 0x0 0x0 0x20000000>; 366 #address-cells = <3>; 367 #size-cells = <2>; 368 device_type = "pci"; 369 bus-range = <0x0 0xff>; 370 ranges = <0x01000000 0x0 0x00008000 0x0 0x18008000 0x0 0x00008000>, 371 <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; 372 373 gmac0: ethernet@3,0 { 374 reg = <0x1800 0x0 0x0 0x0 0x0>; 375 interrupt-parent = <&liointc0>; 376 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 377 <13 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "macirq", "eth_lpi"; 379 status = "disabled"; 380 }; 381 382 gmac1: ethernet@3,1 { 383 reg = <0x1900 0x0 0x0 0x0 0x0>; 384 interrupt-parent = <&liointc0>; 385 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 386 <15 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-names = "macirq", "eth_lpi"; 388 status = "disabled"; 389 }; 390 391 ehci0: usb@4,1 { 392 reg = <0x2100 0x0 0x0 0x0 0x0>; 393 interrupt-parent = <&liointc1>; 394 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 395 status = "disabled"; 396 }; 397 398 ohci0: usb@4,2 { 399 reg = <0x2200 0x0 0x0 0x0 0x0>; 400 interrupt-parent = <&liointc1>; 401 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 402 status = "disabled"; 403 }; 404 405 display@6,0 { 406 reg = <0x3000 0x0 0x0 0x0 0x0>; 407 interrupt-parent = <&liointc0>; 408 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 409 status = "disabled"; 410 }; 411 412 hda@7,0 { 413 reg = <0x3800 0x0 0x0 0x0 0x0>; 414 interrupt-parent = <&liointc0>; 415 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 416 status = "disabled"; 417 }; 418 419 sata: sata@8,0 { 420 reg = <0x4000 0x0 0x0 0x0 0x0>; 421 interrupt-parent = <&liointc0>; 422 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 423 status = "disabled"; 424 }; 425 426 pcie@9,0 { 427 reg = <0x4800 0x0 0x0 0x0 0x0>; 428 #address-cells = <3>; 429 #size-cells = <2>; 430 device_type = "pci"; 431 #interrupt-cells = <1>; 432 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 433 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 0x0 IRQ_TYPE_LEVEL_HIGH>; 434 ranges; 435 }; 436 437 pcie@a,0 { 438 reg = <0x5000 0x0 0x0 0x0 0x0>; 439 #address-cells = <3>; 440 #size-cells = <2>; 441 device_type = "pci"; 442 interrupt-parent = <&liointc1>; 443 #interrupt-cells = <1>; 444 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 445 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>; 446 ranges; 447 }; 448 449 pcie@b,0 { 450 reg = <0x5800 0x0 0x0 0x0 0x0>; 451 #address-cells = <3>; 452 #size-cells = <2>; 453 device_type = "pci"; 454 interrupt-parent = <&liointc1>; 455 #interrupt-cells = <1>; 456 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 457 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>; 458 ranges; 459 }; 460 461 pcie@c,0 { 462 reg = <0x6000 0x0 0x0 0x0 0x0>; 463 #address-cells = <3>; 464 #size-cells = <2>; 465 device_type = "pci"; 466 interrupt-parent = <&liointc1>; 467 #interrupt-cells = <1>; 468 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 469 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>; 470 ranges; 471 }; 472 473 pcie@d,0 { 474 reg = <0x6800 0x0 0x0 0x0 0x0>; 475 #address-cells = <3>; 476 #size-cells = <2>; 477 device_type = "pci"; 478 interrupt-parent = <&liointc1>; 479 #interrupt-cells = <1>; 480 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 481 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>; 482 ranges; 483 }; 484 485 pcie@e,0 { 486 reg = <0x7000 0x0 0x0 0x0 0x0>; 487 #address-cells = <3>; 488 #size-cells = <2>; 489 device_type = "pci"; 490 interrupt-parent = <&liointc1>; 491 #interrupt-cells = <1>; 492 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 493 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>; 494 ranges; 495 }; 496 }; 497 }; 498}; 499