1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
15  * struct zynq_pll - pll clock
16  * @hw:		Handle between common and hardware-specific interfaces
45  * zynq_pll_round_rate() - Round a clock frequency
46  * @hw:		Handle between common and hardware-specific interfaces
48  * @prate:	Clock frequency of parent clock
56 	fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate);  in zynq_pll_determine_rate()
62 	req->rate = req->best_parent_rate * fbdiv;  in zynq_pll_determine_rate()
68  * zynq_pll_recalc_rate() - Recalculate clock frequency
69  * @hw:			Handle between common and hardware-specific interfaces
70  * @parent_rate:	Clock frequency of parent clock
76 	struct zynq_pll *clk = to_zynq_pll(hw);  in zynq_pll_recalc_rate()  local
83 	fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>  in zynq_pll_recalc_rate()
90  * zynq_pll_is_enabled - Check if a clock is enabled
91  * @hw:		Handle between common and hardware-specific interfaces
101 	struct zynq_pll *clk = to_zynq_pll(hw);  in zynq_pll_is_enabled()  local
103 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_is_enabled()
105 	reg = readl(clk->pll_ctrl);  in zynq_pll_is_enabled()
107 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_is_enabled()
113  * zynq_pll_enable - Enable clock
114  * @hw:		Handle between common and hardware-specific interfaces
121 	struct zynq_pll *clk = to_zynq_pll(hw);  in zynq_pll_enable()  local
129 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_enable()
131 	reg = readl(clk->pll_ctrl);  in zynq_pll_enable()
133 	writel(reg, clk->pll_ctrl);  in zynq_pll_enable()
134 	while (!(readl(clk->pll_status) & (1 << clk->lockbit)))  in zynq_pll_enable()
137 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_enable()
143  * zynq_pll_disable - Disable clock
144  * @hw:		Handle between common and hardware-specific interfaces
151 	struct zynq_pll *clk = to_zynq_pll(hw);  in zynq_pll_disable()  local
159 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_disable()
161 	reg = readl(clk->pll_ctrl);  in zynq_pll_disable()
163 	writel(reg, clk->pll_ctrl);  in zynq_pll_disable()
165 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_disable()
177  * clk_register_zynq_pll() - Register PLL with the clock framework
179  * @parent:	Parent clock name
186 struct clk *clk_register_zynq_pll(const char *name, const char *parent,  in clk_register_zynq_pll()  argument
191 	struct clk *clk;  in clk_register_zynq_pll()  local
193 	const char *parent_arr[1] = {parent};  in clk_register_zynq_pll()
205 		return ERR_PTR(-ENOMEM);  in clk_register_zynq_pll()
208 	pll->hw.init = &initd;  in clk_register_zynq_pll()
209 	pll->pll_ctrl = pll_ctrl;  in clk_register_zynq_pll()
210 	pll->pll_status = pll_status;  in clk_register_zynq_pll()
211 	pll->lockbit = lock_index;  in clk_register_zynq_pll()
212 	pll->lock = lock;  in clk_register_zynq_pll()
214 	spin_lock_irqsave(pll->lock, flags);  in clk_register_zynq_pll()
216 	reg = readl(pll->pll_ctrl);  in clk_register_zynq_pll()
218 	writel(reg, pll->pll_ctrl);  in clk_register_zynq_pll()
220 	spin_unlock_irqrestore(pll->lock, flags);  in clk_register_zynq_pll()
222 	clk = clk_register(NULL, &pll->hw);  in clk_register_zynq_pll()
223 	if (WARN_ON(IS_ERR(clk)))  in clk_register_zynq_pll()
226 	return clk;  in clk_register_zynq_pll()
231 	return clk;  in clk_register_zynq_pll()