xref: /linux/arch/loongarch/boot/dts/loongson-2k0500.dtsi (revision 36ec807b627b4c0a0a382f0ae48eac7187d14b2b)
10f66569cSBinbin Zhou// SPDX-License-Identifier: GPL-2.0
20f66569cSBinbin Zhou/*
30f66569cSBinbin Zhou * Copyright (C) 2023 Loongson Technology Corporation Limited
40f66569cSBinbin Zhou */
50f66569cSBinbin Zhou
60f66569cSBinbin Zhou/dts-v1/;
70f66569cSBinbin Zhou
80f66569cSBinbin Zhou#include <dt-bindings/interrupt-controller/irq.h>
9*bd7bc02bSBinbin Zhou#include <dt-bindings/clock/loongson,ls2k-clk.h>
100f66569cSBinbin Zhou
110f66569cSBinbin Zhou/ {
120f66569cSBinbin Zhou	#address-cells = <2>;
130f66569cSBinbin Zhou	#size-cells = <2>;
140f66569cSBinbin Zhou
150f66569cSBinbin Zhou	cpus {
160f66569cSBinbin Zhou		#address-cells = <1>;
170f66569cSBinbin Zhou		#size-cells = <0>;
180f66569cSBinbin Zhou
190f66569cSBinbin Zhou		cpu0: cpu@0 {
200f66569cSBinbin Zhou			compatible = "loongson,la264";
210f66569cSBinbin Zhou			device_type = "cpu";
220f66569cSBinbin Zhou			reg = <0x0>;
23*bd7bc02bSBinbin Zhou			clocks = <&clk LOONGSON2_NODE_CLK>;
240f66569cSBinbin Zhou		};
250f66569cSBinbin Zhou	};
260f66569cSBinbin Zhou
27*bd7bc02bSBinbin Zhou	ref_100m: clock-ref-100m {
280f66569cSBinbin Zhou		compatible = "fixed-clock";
290f66569cSBinbin Zhou		#clock-cells = <0>;
30*bd7bc02bSBinbin Zhou		clock-frequency = <100000000>;
31*bd7bc02bSBinbin Zhou		clock-output-names = "ref_100m";
320f66569cSBinbin Zhou	};
330f66569cSBinbin Zhou
340f66569cSBinbin Zhou	cpuintc: interrupt-controller {
350f66569cSBinbin Zhou		compatible = "loongson,cpu-interrupt-controller";
360f66569cSBinbin Zhou		#interrupt-cells = <1>;
370f66569cSBinbin Zhou		interrupt-controller;
380f66569cSBinbin Zhou	};
390f66569cSBinbin Zhou
40*bd7bc02bSBinbin Zhou	thermal-zones {
41*bd7bc02bSBinbin Zhou		cpu-thermal {
42*bd7bc02bSBinbin Zhou			polling-delay-passive = <1000>;
43*bd7bc02bSBinbin Zhou			polling-delay = <5000>;
44*bd7bc02bSBinbin Zhou			thermal-sensors = <&tsensor 0>;
45*bd7bc02bSBinbin Zhou
46*bd7bc02bSBinbin Zhou			trips {
47*bd7bc02bSBinbin Zhou				cpu-alert {
48*bd7bc02bSBinbin Zhou					temperature = <33000>;
49*bd7bc02bSBinbin Zhou					hysteresis = <2000>;
50*bd7bc02bSBinbin Zhou					type = "active";
51*bd7bc02bSBinbin Zhou				};
52*bd7bc02bSBinbin Zhou
53*bd7bc02bSBinbin Zhou				cpu-crit {
54*bd7bc02bSBinbin Zhou					temperature = <85000>;
55*bd7bc02bSBinbin Zhou					hysteresis = <5000>;
56*bd7bc02bSBinbin Zhou					type = "critical";
57*bd7bc02bSBinbin Zhou				};
58*bd7bc02bSBinbin Zhou			};
59*bd7bc02bSBinbin Zhou		};
60*bd7bc02bSBinbin Zhou	};
61*bd7bc02bSBinbin Zhou
620f66569cSBinbin Zhou	bus@10000000 {
630f66569cSBinbin Zhou		compatible = "simple-bus";
640f66569cSBinbin Zhou		ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
650f66569cSBinbin Zhou			 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
660f66569cSBinbin Zhou			 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
670f66569cSBinbin Zhou			 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
680f66569cSBinbin Zhou			 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
690f66569cSBinbin Zhou		#address-cells = <2>;
700f66569cSBinbin Zhou		#size-cells = <2>;
710f66569cSBinbin Zhou
720f66569cSBinbin Zhou		isa@16400000 {
730f66569cSBinbin Zhou			compatible = "isa";
740f66569cSBinbin Zhou			#size-cells = <1>;
750f66569cSBinbin Zhou			#address-cells = <2>;
760f66569cSBinbin Zhou			ranges = <1 0x0 0x0 0x16400000 0x4000>;
770f66569cSBinbin Zhou		};
780f66569cSBinbin Zhou
79*bd7bc02bSBinbin Zhou		clk: clock-controller@1fe10400 {
80*bd7bc02bSBinbin Zhou			compatible = "loongson,ls2k0500-clk";
81*bd7bc02bSBinbin Zhou			reg = <0x0 0x1fe10400 0x0 0x2c>;
82*bd7bc02bSBinbin Zhou			#clock-cells = <1>;
83*bd7bc02bSBinbin Zhou			clocks = <&ref_100m>;
84*bd7bc02bSBinbin Zhou			clock-names = "ref_100m";
85*bd7bc02bSBinbin Zhou		};
86*bd7bc02bSBinbin Zhou
87*bd7bc02bSBinbin Zhou		dma-controller@1fe10c00 {
88*bd7bc02bSBinbin Zhou			compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
89*bd7bc02bSBinbin Zhou			reg = <0 0x1fe10c00 0 0x8>;
90*bd7bc02bSBinbin Zhou			interrupt-parent = <&eiointc>;
91*bd7bc02bSBinbin Zhou			interrupts = <67>;
92*bd7bc02bSBinbin Zhou			clocks = <&clk LOONGSON2_APB_CLK>;
93*bd7bc02bSBinbin Zhou			#dma-cells = <1>;
94*bd7bc02bSBinbin Zhou			status = "disabled";
95*bd7bc02bSBinbin Zhou		};
96*bd7bc02bSBinbin Zhou
97*bd7bc02bSBinbin Zhou		dma-controller@1fe10c10 {
98*bd7bc02bSBinbin Zhou			compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
99*bd7bc02bSBinbin Zhou			reg = <0 0x1fe10c10 0 0x8>;
100*bd7bc02bSBinbin Zhou			interrupt-parent = <&eiointc>;
101*bd7bc02bSBinbin Zhou			interrupts = <68>;
102*bd7bc02bSBinbin Zhou			clocks = <&clk LOONGSON2_APB_CLK>;
103*bd7bc02bSBinbin Zhou			#dma-cells = <1>;
104*bd7bc02bSBinbin Zhou			status = "disabled";
105*bd7bc02bSBinbin Zhou		};
106*bd7bc02bSBinbin Zhou
107*bd7bc02bSBinbin Zhou		dma-controller@1fe10c20 {
108*bd7bc02bSBinbin Zhou			compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
109*bd7bc02bSBinbin Zhou			reg = <0 0x1fe10c20 0 0x8>;
110*bd7bc02bSBinbin Zhou			interrupt-parent = <&eiointc>;
111*bd7bc02bSBinbin Zhou			interrupts = <69>;
112*bd7bc02bSBinbin Zhou			clocks = <&clk LOONGSON2_APB_CLK>;
113*bd7bc02bSBinbin Zhou			#dma-cells = <1>;
114*bd7bc02bSBinbin Zhou			status = "disabled";
115*bd7bc02bSBinbin Zhou		};
116*bd7bc02bSBinbin Zhou
117*bd7bc02bSBinbin Zhou		dma-controller@1fe10c30 {
118*bd7bc02bSBinbin Zhou			compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
119*bd7bc02bSBinbin Zhou			reg = <0 0x1fe10c30 0 0x8>;
120*bd7bc02bSBinbin Zhou			interrupt-parent = <&eiointc>;
121*bd7bc02bSBinbin Zhou			interrupts = <70>;
122*bd7bc02bSBinbin Zhou			clocks = <&clk LOONGSON2_APB_CLK>;
123*bd7bc02bSBinbin Zhou			#dma-cells = <1>;
124*bd7bc02bSBinbin Zhou			status = "disabled";
125*bd7bc02bSBinbin Zhou		};
126*bd7bc02bSBinbin Zhou
1270f66569cSBinbin Zhou		liointc0: interrupt-controller@1fe11400 {
1280f66569cSBinbin Zhou			compatible = "loongson,liointc-2.0";
1290f66569cSBinbin Zhou			reg = <0x0 0x1fe11400 0x0 0x40>,
1300f66569cSBinbin Zhou			      <0x0 0x1fe11040 0x0 0x8>;
1310f66569cSBinbin Zhou			reg-names = "main", "isr0";
1320f66569cSBinbin Zhou
1330f66569cSBinbin Zhou			interrupt-controller;
1340f66569cSBinbin Zhou			#interrupt-cells = <2>;
1350f66569cSBinbin Zhou			interrupt-parent = <&cpuintc>;
1360f66569cSBinbin Zhou			interrupts = <2>;
1370f66569cSBinbin Zhou			interrupt-names = "int0";
1380f66569cSBinbin Zhou
1390f66569cSBinbin Zhou			loongson,parent_int_map = <0xffffffff>, /* int0 */
1400f66569cSBinbin Zhou						  <0x00000000>, /* int1 */
1410f66569cSBinbin Zhou						  <0x00000000>, /* int2 */
1420f66569cSBinbin Zhou						  <0x00000000>; /* int3 */
1430f66569cSBinbin Zhou		};
1440f66569cSBinbin Zhou
1450f66569cSBinbin Zhou		liointc1: interrupt-controller@1fe11440 {
1460f66569cSBinbin Zhou			compatible = "loongson,liointc-2.0";
1470f66569cSBinbin Zhou			reg = <0x0 0x1fe11440 0x0 0x40>,
1480f66569cSBinbin Zhou			      <0x0 0x1fe11048 0x0 0x8>;
1490f66569cSBinbin Zhou			reg-names = "main", "isr0";
1500f66569cSBinbin Zhou
1510f66569cSBinbin Zhou			interrupt-controller;
1520f66569cSBinbin Zhou			#interrupt-cells = <2>;
1530f66569cSBinbin Zhou			interrupt-parent = <&cpuintc>;
1540f66569cSBinbin Zhou			interrupts = <4>;
1550f66569cSBinbin Zhou			interrupt-names = "int2";
1560f66569cSBinbin Zhou
1570f66569cSBinbin Zhou			loongson,parent_int_map = <0x00000000>, /* int0 */
1580f66569cSBinbin Zhou						  <0x00000000>, /* int1 */
1590f66569cSBinbin Zhou						  <0xffffffff>, /* int2 */
1600f66569cSBinbin Zhou						  <0x00000000>; /* int3 */
1610f66569cSBinbin Zhou		};
1620f66569cSBinbin Zhou
1630f66569cSBinbin Zhou		eiointc: interrupt-controller@1fe11600 {
1640f66569cSBinbin Zhou			compatible = "loongson,ls2k0500-eiointc";
1650f66569cSBinbin Zhou			reg = <0x0 0x1fe11600 0x0 0xea00>;
1660f66569cSBinbin Zhou			interrupt-controller;
1670f66569cSBinbin Zhou			#interrupt-cells = <1>;
1680f66569cSBinbin Zhou			interrupt-parent = <&cpuintc>;
1690f66569cSBinbin Zhou			interrupts = <3>;
1700f66569cSBinbin Zhou		};
1710f66569cSBinbin Zhou
1720f66569cSBinbin Zhou		gmac0: ethernet@1f020000 {
1730f66569cSBinbin Zhou			compatible = "snps,dwmac-3.70a";
1740f66569cSBinbin Zhou			reg = <0x0 0x1f020000 0x0 0x10000>;
1750f66569cSBinbin Zhou			interrupt-parent = <&liointc0>;
1760f66569cSBinbin Zhou			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
1770f66569cSBinbin Zhou			interrupt-names = "macirq";
1780f66569cSBinbin Zhou			status = "disabled";
1790f66569cSBinbin Zhou		};
1800f66569cSBinbin Zhou
1810f66569cSBinbin Zhou		gmac1: ethernet@1f030000 {
1820f66569cSBinbin Zhou			compatible = "snps,dwmac-3.70a";
1830f66569cSBinbin Zhou			reg = <0x0 0x1f030000 0x0 0x10000>;
1840f66569cSBinbin Zhou			interrupt-parent = <&liointc0>;
1850f66569cSBinbin Zhou			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
1860f66569cSBinbin Zhou			interrupt-names = "macirq";
1870f66569cSBinbin Zhou			status = "disabled";
1880f66569cSBinbin Zhou		};
1890f66569cSBinbin Zhou
1900f66569cSBinbin Zhou		sata: sata@1f040000 {
1910f66569cSBinbin Zhou			compatible = "snps,spear-ahci";
1920f66569cSBinbin Zhou			reg = <0x0 0x1f040000 0x0 0x10000>;
1930f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
1940f66569cSBinbin Zhou			interrupts = <75>;
1950f66569cSBinbin Zhou			status = "disabled";
1960f66569cSBinbin Zhou		};
1970f66569cSBinbin Zhou
1980f66569cSBinbin Zhou		ehci0: usb@1f050000 {
1990f66569cSBinbin Zhou			compatible = "generic-ehci";
2000f66569cSBinbin Zhou			reg = <0x0 0x1f050000 0x0 0x8000>;
2010f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2020f66569cSBinbin Zhou			interrupts = <71>;
2030f66569cSBinbin Zhou			status = "disabled";
2040f66569cSBinbin Zhou		};
2050f66569cSBinbin Zhou
2060f66569cSBinbin Zhou		ohci0: usb@1f058000 {
2070f66569cSBinbin Zhou			compatible = "generic-ohci";
2080f66569cSBinbin Zhou			reg = <0x0 0x1f058000 0x0 0x8000>;
2090f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2100f66569cSBinbin Zhou			interrupts = <72>;
2110f66569cSBinbin Zhou			status = "disabled";
2120f66569cSBinbin Zhou		};
2130f66569cSBinbin Zhou
214*bd7bc02bSBinbin Zhou		tsensor: thermal-sensor@1fe11500 {
215*bd7bc02bSBinbin Zhou			compatible = "loongson,ls2k0500-thermal", "loongson,ls2k1000-thermal";
216*bd7bc02bSBinbin Zhou			reg = <0x0 0x1fe11500 0x0 0x30>;
217*bd7bc02bSBinbin Zhou			interrupt-parent = <&liointc0>;
218*bd7bc02bSBinbin Zhou			interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
219*bd7bc02bSBinbin Zhou			#thermal-sensor-cells = <1>;
220*bd7bc02bSBinbin Zhou		};
221*bd7bc02bSBinbin Zhou
2220f66569cSBinbin Zhou		uart0: serial@1ff40800 {
2230f66569cSBinbin Zhou			compatible = "ns16550a";
2240f66569cSBinbin Zhou			reg = <0x0 0x1ff40800 0x0 0x10>;
2250f66569cSBinbin Zhou			clock-frequency = <100000000>;
2260f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2270f66569cSBinbin Zhou			interrupts = <2>;
2280f66569cSBinbin Zhou			no-loopback-test;
2290f66569cSBinbin Zhou			status = "disabled";
2300f66569cSBinbin Zhou		};
2310f66569cSBinbin Zhou
2320f66569cSBinbin Zhou		i2c0: i2c@1ff48000 {
2330f66569cSBinbin Zhou			compatible = "loongson,ls2k-i2c";
2340f66569cSBinbin Zhou			reg = <0x0 0x1ff48000 0x0 0x0800>;
2350f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2360f66569cSBinbin Zhou			interrupts = <14>;
2370f66569cSBinbin Zhou			status = "disabled";
2380f66569cSBinbin Zhou		};
2390f66569cSBinbin Zhou
2400f66569cSBinbin Zhou		i2c@1ff48800 {
2410f66569cSBinbin Zhou			compatible = "loongson,ls2k-i2c";
2420f66569cSBinbin Zhou			reg = <0x0 0x1ff48800 0x0 0x0800>;
2430f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2440f66569cSBinbin Zhou			interrupts = <15>;
2450f66569cSBinbin Zhou			status = "disabled";
2460f66569cSBinbin Zhou		};
2470f66569cSBinbin Zhou
2480f66569cSBinbin Zhou		i2c@1ff49000 {
2490f66569cSBinbin Zhou			compatible = "loongson,ls2k-i2c";
2500f66569cSBinbin Zhou			reg = <0x0 0x1ff49000 0x0 0x0800>;
2510f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2520f66569cSBinbin Zhou			interrupts = <16>;
2530f66569cSBinbin Zhou			status = "disabled";
2540f66569cSBinbin Zhou		};
2550f66569cSBinbin Zhou
2560f66569cSBinbin Zhou		i2c@1ff49800 {
2570f66569cSBinbin Zhou			compatible = "loongson,ls2k-i2c";
2580f66569cSBinbin Zhou			reg = <0x0 0x1ff49800 0x0 0x0800>;
2590f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2600f66569cSBinbin Zhou			interrupts = <17>;
2610f66569cSBinbin Zhou			status = "disabled";
2620f66569cSBinbin Zhou		};
2630f66569cSBinbin Zhou
2640f66569cSBinbin Zhou		i2c@1ff4a000 {
2650f66569cSBinbin Zhou			compatible = "loongson,ls2k-i2c";
2660f66569cSBinbin Zhou			reg = <0x0 0x1ff4a000 0x0 0x0800>;
2670f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2680f66569cSBinbin Zhou			interrupts = <18>;
2690f66569cSBinbin Zhou			status = "disabled";
2700f66569cSBinbin Zhou		};
2710f66569cSBinbin Zhou
2720f66569cSBinbin Zhou		i2c@1ff4a800 {
2730f66569cSBinbin Zhou			compatible = "loongson,ls2k-i2c";
2740f66569cSBinbin Zhou			reg = <0x0 0x1ff4a800 0x0 0x0800>;
2750f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2760f66569cSBinbin Zhou			interrupts = <19>;
2770f66569cSBinbin Zhou			status = "disabled";
2780f66569cSBinbin Zhou		};
2790f66569cSBinbin Zhou
2800f66569cSBinbin Zhou		pmc: power-management@1ff6c000 {
2810f66569cSBinbin Zhou			compatible = "loongson,ls2k0500-pmc", "syscon";
2820f66569cSBinbin Zhou			reg = <0x0 0x1ff6c000 0x0 0x58>;
2830f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
2840f66569cSBinbin Zhou			interrupts = <56>;
2850f66569cSBinbin Zhou			loongson,suspend-address = <0x0 0x1c000500>;
2860f66569cSBinbin Zhou
2870f66569cSBinbin Zhou			syscon-reboot {
2880f66569cSBinbin Zhou				compatible = "syscon-reboot";
2890f66569cSBinbin Zhou				offset = <0x30>;
2900f66569cSBinbin Zhou				mask = <0x1>;
2910f66569cSBinbin Zhou			};
2920f66569cSBinbin Zhou
2930f66569cSBinbin Zhou			syscon-poweroff {
2940f66569cSBinbin Zhou				compatible = "syscon-poweroff";
2950f66569cSBinbin Zhou				regmap = <&pmc>;
2960f66569cSBinbin Zhou				offset = <0x14>;
2970f66569cSBinbin Zhou				mask = <0x3c00>;
2980f66569cSBinbin Zhou				value = <0x3c00>;
2990f66569cSBinbin Zhou			};
3000f66569cSBinbin Zhou		};
3010f66569cSBinbin Zhou
3020f66569cSBinbin Zhou		rtc0: rtc@1ff6c100 {
3030f66569cSBinbin Zhou			compatible = "loongson,ls2k0500-rtc", "loongson,ls7a-rtc";
3040f66569cSBinbin Zhou			reg = <0x0 0x1ff6c100 0x0 0x100>;
3050f66569cSBinbin Zhou			interrupt-parent = <&eiointc>;
3060f66569cSBinbin Zhou			interrupts = <35>;
3070f66569cSBinbin Zhou			status = "disabled";
3080f66569cSBinbin Zhou		};
3090f66569cSBinbin Zhou
3100f66569cSBinbin Zhou		pcie@1a000000 {
3110f66569cSBinbin Zhou			compatible = "loongson,ls2k-pci";
3120f66569cSBinbin Zhou			reg = <0x0 0x1a000000 0x0 0x02000000>,
3130f66569cSBinbin Zhou			      <0xfe 0x0 0x0 0x20000000>;
3140f66569cSBinbin Zhou			#address-cells = <3>;
3150f66569cSBinbin Zhou			#size-cells = <2>;
3160f66569cSBinbin Zhou			device_type = "pci";
3170f66569cSBinbin Zhou			bus-range = <0x0 0x5>;
3180f66569cSBinbin Zhou			ranges = <0x01000000 0x0 0x00004000 0x0 0x16404000 0x0 0x00004000>,
3190f66569cSBinbin Zhou				 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
3200f66569cSBinbin Zhou
3210f66569cSBinbin Zhou			pcie@0,0 {
3220f66569cSBinbin Zhou				reg = <0x0000 0x0 0x0 0x0 0x0>;
3230f66569cSBinbin Zhou				#address-cells = <3>;
3240f66569cSBinbin Zhou				#size-cells = <2>;
3250f66569cSBinbin Zhou				device_type = "pci";
3260f66569cSBinbin Zhou				interrupt-parent = <&eiointc>;
3270f66569cSBinbin Zhou				#interrupt-cells = <1>;
3280f66569cSBinbin Zhou				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
3290f66569cSBinbin Zhou				interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 81>;
3300f66569cSBinbin Zhou				ranges;
3310f66569cSBinbin Zhou			};
3320f66569cSBinbin Zhou
3330f66569cSBinbin Zhou			pcie@1,0 {
3340f66569cSBinbin Zhou				reg = <0x0800 0x0 0x0 0x0 0x0>;
3350f66569cSBinbin Zhou				#address-cells = <3>;
3360f66569cSBinbin Zhou				#size-cells = <2>;
3370f66569cSBinbin Zhou				device_type = "pci";
3380f66569cSBinbin Zhou				interrupt-parent = <&eiointc>;
3390f66569cSBinbin Zhou				#interrupt-cells = <1>;
3400f66569cSBinbin Zhou				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
3410f66569cSBinbin Zhou				interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 82>;
3420f66569cSBinbin Zhou				ranges;
3430f66569cSBinbin Zhou			};
3440f66569cSBinbin Zhou		};
3450f66569cSBinbin Zhou	};
3460f66569cSBinbin Zhou};
347