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/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
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/linux/Documentation/devicetree/bindings/soc/microchip/
H A Dmicrochip,mpfs-sys-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <conor.dooley@microchip.com>
16 eNVM contents etc. More information on these services can be found online, at
17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
27 const: microchip,mpfs-sys-controller
29 microchip,bitstream-flash:
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/linux/drivers/usb/musb/
H A Dmpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * PolarFire SoC (MPFS) MUSB Glue Layer
5 * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
11 #include <linux/dma-mapping.h>
58 * connect. They can trigger transient overcurrent conditions in mpfs_musb_set_vbus()
61 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); in mpfs_musb_set_vbus()
64 musb->is_active = 1; in mpfs_musb_set_vbus()
65 musb->xceiv->otg->default_a = 1; in mpfs_musb_set_vbus()
66 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; in mpfs_musb_set_vbus()
70 musb->is_active = 0; in mpfs_musb_set_vbus()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # USB Dual Role (OTG-ready) Controller Drivers
7 # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
27 module will be called "musb-hdrc".
74 tristate "DA8xx/OMAP-L1x"
124 will be called mpfs.
136 you can still disable it at run time using the "use_dma=n" module
160 depends on USB_MUSB_TUSB6010 = USB_MUSB_HDRC # both built-in or both modules
/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
H A Dkconfig.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
10 | mlx5 core is modular and most of the major mlx5 core driver features can be selected (compiled in…
26 | The driver can be enabled by choosing CONFIG_MLX5_CORE=y/m in kernel config.
34 | built-in into mlx5_core.ko.
39 …g (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-…
53 | Flow-based classifiers, such as those registered through
54 | `tc-flower(8)`, are processed by the device, rather than the
61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
62 | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
67 | Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`.
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/linux/drivers/firmware/microchip/
H A Dmpfs-auto-update.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (c) 2022-2023 Microchip Corporation. All rights reserved.
21 #include <soc/microchip/mpfs.h>
44 * |------------------------------| 0x0000000
47 * |------------------------------| 0x0000400
51 * |------------------------------| 0x0100400
54 * |------------------------------| 0x1500400
57 * |------------------------------| 0x2900400
59 * | Reserved for multi-image IAP |
61 * |------------------------------| 0x3D00400
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/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
94 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
97 If compiled as module, it will be called reset-gpio.
146 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
155 Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
201 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
231 Raspberry Pi 4's co-processor controls some of the board's HW
234 interfacing with RPi4's co-processor and model these firmware
268 that can be asserted and deasserted by toggling bits in a contiguous,
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/linux/drivers/i2c/busses/
H A Di2c-microchip-corei2c.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018-2022 Microchip Corporation. All rights reserved.
93 * struct mchp_corei2c_dev - Microchip CoreI2C device private data
131 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable()
134 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable()
139 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable()
142 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable()
153 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_stop()
156 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_stop()
181 return -EINVAL; in mchp_corei2c_set_divisor()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Deswitch.h14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
45 #include "lib/mpfs.h"
87 ((esw)->fdb_table.offloads.esw_chains_priv)
114 /* Group to add default match-all FTE entry to tag ingress
187 dl_port->vport = vport; in mlx5_devlink_port_init()
197 return mlx5_devlink_port_get(dl_port)->vport; in mlx5_devlink_port_vport_get()
200 #define MLX5_VHCA_ID_INVALID (-1)
203 ((vport)->vhca_id == MLX5_VHCA_ID_INVALID)
227 /* Protected with the E-Switch qos domain lock. The Vport QoS can
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H A Dmain.c2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
54 #include "lib/mpfs.h"
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
197 fw_initializing = ioread32be(&dev->iseg->initializing); in wait_fw_init()
203 return -ETIMEDOUT; in wait_fw_init()
205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { in wait_fw_init()
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/linux/drivers/rtc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
69 one can sleep when setting time, because it runs in the workqueue
129 can be accessed as /dev/rtc, which is a name
141 once-per-second update interrupts, used for synchronization.
151 RTC test driver. It's a software RTC which can be
158 This driver can also be built as a module. If so, the module
159 will be called rtc-test.
172 This driver can also be built as a module. If so, the module
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/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
23 #include <linux/dma-mapping.h>
37 #include <linux/firmware/xlnx-zynqmp.h>
61 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
72 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
88 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
127 switch (bp->hw_dma_cap) { in macb_dma_desc_get_size()
152 switch (bp->hw_dma_cap) { in macb_adj_dma_desc_idx()
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