xref: /linux/drivers/mailbox/Kconfig (revision a06079511167984f7d25ff09fdfeb2f1582c85dd)
1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig MAILBOX
3	bool "Mailbox Hardware Support"
4	help
5	  Mailbox is a framework to control hardware communication between
6	  on-chip processors through queued messages and interrupt driven
7	  signals. Say Y if your platform supports hardware mailboxes.
8
9if MAILBOX
10
11config ARM_MHU
12	tristate "ARM MHU Mailbox"
13	depends on ARM_AMBA
14	help
15	  Say Y here if you want to build the ARM MHU controller driver.
16	  The controller has 3 mailbox channels, the last of which can be
17	  used in Secure mode only.
18
19config ARM_MHU_V2
20	tristate "ARM MHUv2 Mailbox"
21	depends on ARM_AMBA
22	help
23	  Say Y here if you want to build the ARM MHUv2 controller driver,
24	  which provides unidirectional mailboxes between processing elements.
25
26config ARM_MHU_V3
27	tristate "ARM MHUv3 Mailbox"
28	depends on ARM64 || COMPILE_TEST
29	depends on HAS_IOMEM || COMPILE_TEST
30	depends on OF
31	help
32	  Say Y here if you want to build the ARM MHUv3 controller driver,
33	  which provides unidirectional mailboxes between processing elements.
34
35	  ARM MHUv3 controllers can implement a varying number of extensions
36	  that provides different means of transports: supported extensions
37	  will be discovered and possibly managed at probe-time.
38
39config CV1800_MBOX
40	tristate "cv1800 mailbox"
41	depends on ARCH_SOPHGO || COMPILE_TEST
42	help
43	  Mailbox driver implementation for Sophgo CV18XX SoCs. This driver
44	  can be used to send message between different processors in SoC. Any
45	  processer can write data in a channel, and set co-responding register
46	  to raise interrupt to notice another processor, and it is allowed to
47	  send data to itself.
48
49config EXYNOS_MBOX
50	tristate "Exynos Mailbox"
51	depends on ARCH_EXYNOS || COMPILE_TEST
52	help
53	  Say Y here if you want to build the Samsung Exynos Mailbox controller
54	  driver. The controller has 16 flag bits for hardware interrupt
55	  generation and a shared register for passing mailbox messages.
56	  When the controller is used by the ACPM interface the shared register
57	  is ignored and the mailbox controller acts as a doorbell that raises
58	  the interrupt to the ACPM firmware.
59
60config IMX_MBOX
61	tristate "i.MX Mailbox"
62	depends on ARCH_MXC || COMPILE_TEST
63	help
64	  Mailbox implementation for i.MX Messaging Unit (MU).
65
66config PLATFORM_MHU
67	tristate "Platform MHU Mailbox"
68	depends on OF
69	depends on HAS_IOMEM
70	help
71	  Say Y here if you want to build a platform specific variant MHU
72	  controller driver.
73	  The controller has a maximum of 3 mailbox channels, the last of
74	  which can be used in Secure mode only.
75
76config PL320_MBOX
77	bool "ARM PL320 Mailbox"
78	depends on ARM_AMBA
79	help
80	  An implementation of the ARM PL320 Interprocessor Communication
81	  Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
82	  send short messages between Highbank's A9 cores and the EnergyCore
83	  Management Engine, primarily for cpufreq. Say Y here if you want
84	  to use the PL320 IPCM support.
85
86config ARMADA_37XX_RWTM_MBOX
87	tristate "Armada 37xx rWTM BIU Mailbox"
88	depends on ARCH_MVEBU || COMPILE_TEST
89	depends on OF
90	help
91	  Mailbox implementation for communication with the the firmware
92	  running on the Cortex-M3 rWTM secure processor of the Armada 37xx
93	  SOC. Say Y here if you are building for such a device (for example
94	  the Turris Mox router).
95
96config OMAP2PLUS_MBOX
97	tristate "OMAP2+ Mailbox framework support"
98	depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST
99	help
100	  Mailbox implementation for OMAP family chips with hardware for
101	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
102	  OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
103	  want to use OMAP2+ Mailbox framework support.
104
105config ROCKCHIP_MBOX
106	bool "Rockchip Soc Integrated Mailbox Support"
107	depends on ARCH_ROCKCHIP || COMPILE_TEST
108	help
109	  This driver provides support for inter-processor communication
110	  between CPU cores and MCU processor on Some Rockchip SOCs.
111	  Please check it that the Soc you use have Mailbox hardware.
112	  Say Y here if you want to use the Rockchip Mailbox support.
113
114config PCC
115	bool "Platform Communication Channel Driver"
116	depends on ACPI
117	default n
118	help
119	  ACPI 5.0+ spec defines a generic mode of communication
120	  between the OS and a platform such as the BMC. This medium
121	  (PCC) is typically used by CPPC (ACPI CPU Performance management),
122	  RAS (ACPI reliability protocol) and MPST (ACPI Memory power
123	  states). Select this driver if your platform implements the
124	  PCC clients mentioned above.
125
126config ALTERA_MBOX
127	tristate "Altera Mailbox"
128	depends on HAS_IOMEM
129	help
130	  An implementation of the Altera Mailbox soft core. It is used
131	  to send message between processors. Say Y here if you want to use the
132	  Altera mailbox support.
133
134config BCM2835_MBOX
135	tristate "BCM2835 Mailbox"
136	depends on ARCH_BCM2835
137	help
138	  An implementation of the BCM2385 Mailbox.  It is used to invoke
139	  the services of the Videocore. Say Y here if you want to use the
140	  BCM2835 Mailbox.
141
142config STI_MBOX
143	tristate "STI Mailbox framework support"
144	depends on ARCH_STI && OF
145	help
146	  Mailbox implementation for STMicroelectonics family chips with
147	  hardware for interprocessor communication.
148
149config TI_MESSAGE_MANAGER
150	tristate "Texas Instruments Message Manager Driver"
151	depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
152	default ARCH_K3
153	help
154	  An implementation of Message Manager slave driver for Keystone
155	  and K3 architecture SoCs from Texas Instruments. Message Manager
156	  is a communication entity found on few of Texas Instrument's keystone
157	  and K3 architecture SoCs. These may be used for communication between
158	  multiple processors within the SoC. Select this driver if your
159	  platform has support for the hardware block.
160
161config HI3660_MBOX
162	tristate "Hi3660 Mailbox" if EXPERT
163	depends on (ARCH_HISI || COMPILE_TEST)
164	depends on OF
165	default ARCH_HISI
166	help
167	  An implementation of the hi3660 mailbox. It is used to send message
168	  between application processors and other processors/MCU/DSP. Select
169	  Y here if you want to use Hi3660 mailbox controller.
170
171config HI6220_MBOX
172	tristate "Hi6220 Mailbox" if EXPERT
173	depends on (ARCH_HISI || COMPILE_TEST)
174	depends on OF
175	default ARCH_HISI
176	help
177	  An implementation of the hi6220 mailbox. It is used to send message
178	  between application processors and MCU. Say Y here if you want to
179	  build Hi6220 mailbox controller driver.
180
181config MAILBOX_TEST
182	tristate "Mailbox Test Client"
183	depends on OF
184	depends on HAS_IOMEM
185	help
186	  Test client to help with testing new Controller driver
187	  implementations.
188
189config POLARFIRE_SOC_MAILBOX
190	tristate "PolarFire SoC (MPFS) Mailbox"
191	depends on HAS_IOMEM
192	depends on MFD_SYSCON
193	depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
194	help
195	  This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
196
197	  To compile this driver as a module, choose M here. the
198	  module will be called mailbox-mpfs.
199
200	  If unsure, say N.
201
202config MCHP_SBI_IPC_MBOX
203	tristate "Microchip Inter-processor Communication (IPC) SBI driver"
204	depends on RISCV_SBI
205	depends on ARCH_MICROCHIP || COMPILE_TEST
206	help
207	  Mailbox implementation for Microchip devices with an
208	  Inter-process communication (IPC) controller.
209
210	  To compile this driver as a module, choose M here. the
211	  module will be called mailbox-mchp-ipc-sbi.
212
213	  If unsure, say N.
214
215config QCOM_APCS_IPC
216	tristate "Qualcomm APCS IPC driver"
217	depends on ARCH_QCOM || COMPILE_TEST
218	help
219	  Say y here to enable support for the APCS IPC mailbox driver,
220	  providing an interface for invoking the inter-process communication
221	  signals from the application processor to other masters.
222
223config TEGRA_HSP_MBOX
224	bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
225	depends on ARCH_TEGRA
226	help
227	  The Tegra HSP driver is used for the interprocessor communication
228	  between different remote processors and host processors on Tegra186
229	  and later SoCs. Say Y here if you want to have this support.
230	  If unsure say N.
231
232config XGENE_SLIMPRO_MBOX
233	tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
234	depends on ARCH_XGENE
235	help
236	  An implementation of the APM X-Gene Interprocessor Communication
237	  Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
238	  It is used to send short messages between ARM64-bit cores and
239	  the SLIMpro Management Engine, primarily for PM. Say Y here if you
240	  want to use the APM X-Gene SLIMpro IPCM support.
241
242config BCM_PDC_MBOX
243	tristate "Broadcom FlexSparx DMA Mailbox"
244	depends on ARCH_BCM_IPROC || COMPILE_TEST
245	help
246	  Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
247	  which provides access to various offload engines on Broadcom
248	  SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
249
250config BCM_FLEXRM_MBOX
251	tristate "Broadcom FlexRM Mailbox"
252	depends on ARM64
253	depends on ARCH_BCM_IPROC || COMPILE_TEST
254	select GENERIC_MSI_IRQ
255	default m if ARCH_BCM_IPROC
256	help
257	  Mailbox implementation of the Broadcom FlexRM ring manager,
258	  which provides access to various offload engines on Broadcom
259	  SoCs. Say Y here if you want to use the Broadcom FlexRM.
260
261config STM32_IPCC
262	tristate "STM32 IPCC Mailbox"
263	depends on MACH_STM32MP157 || COMPILE_TEST
264	help
265	  Mailbox implementation for STMicroelectonics STM32 family chips
266	  with hardware for Inter-Processor Communication Controller (IPCC)
267	  between processors. Say Y here if you want to have this support.
268
269config MTK_ADSP_MBOX
270	tristate "MediaTek ADSP Mailbox Controller"
271	depends on ARCH_MEDIATEK || COMPILE_TEST
272	help
273          Say yes here to add support for "MediaTek ADSP Mailbox Controller.
274          This mailbox driver is used to send notification or short message
275          between processors with ADSP. It will place the message to share
276	  buffer and will access the ipc control.
277
278config MTK_CMDQ_MBOX
279	tristate "MediaTek CMDQ Mailbox Support"
280	depends on ARCH_MEDIATEK || COMPILE_TEST
281	select MTK_INFRACFG
282	help
283	  Say yes here to add support for the MediaTek Command Queue (CMDQ)
284	  mailbox driver. The CMDQ is used to help read/write registers with
285	  critical time limitation, such as updating display configuration
286	  during the vblank.
287
288config ZYNQMP_IPI_MBOX
289	tristate "Xilinx ZynqMP IPI Mailbox"
290	depends on ARCH_ZYNQMP && OF
291	help
292	  Say yes here to add support for Xilinx IPI mailbox driver.
293	  This mailbox driver is used to send notification or short message
294	  between processors with Xilinx ZynqMP IPI. It will place the
295	  message to the IPI buffer and will access the IPI control
296	  registers to kick the other processor or enquire status.
297
298config SUN6I_MSGBOX
299	tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
300	depends on ARCH_SUNXI || COMPILE_TEST
301	default ARCH_SUNXI
302	help
303	  Mailbox implementation for the hardware message box present in
304	  various Allwinner SoCs. This mailbox is used for communication
305	  between the application CPUs and the power management coprocessor.
306
307config SPRD_MBOX
308	tristate "Spreadtrum Mailbox"
309	depends on ARCH_SPRD || COMPILE_TEST
310	help
311	  Mailbox driver implementation for the Spreadtrum platform. It is used
312	  to send message between application processors and MCU. Say Y here if
313	  you want to build the Spreatrum mailbox controller driver.
314
315config QCOM_CPUCP_MBOX
316	tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
317	depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT
318	help
319	  Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
320	  controller driver enables communication between AP and CPUCP. Say
321	  Y here if you want to build this driver.
322
323config QCOM_IPCC
324	tristate "Qualcomm Technologies, Inc. IPCC driver"
325	depends on ARCH_QCOM || COMPILE_TEST
326	help
327	  Qualcomm Technologies, Inc. Inter-Processor Communication Controller
328	  (IPCC) driver for MSM devices. The driver provides mailbox support for
329	  sending interrupts to the clients. On the other hand, the driver also
330	  acts as an interrupt controller for receiving interrupts from clients.
331	  Say Y here if you want to build this driver.
332
333config THEAD_TH1520_MBOX
334	tristate "T-head TH1520 Mailbox"
335	depends on ARCH_THEAD || COMPILE_TEST
336	help
337	  Mailbox driver implementation for the Thead TH-1520 platform. Enables
338	  two cores within the SoC to communicate and coordinate by passing
339	  messages. Could be used to communicate between E910 core, on which the
340	  kernel is running, and E902 core used for power management among other
341	  things.
342
343endif
344