/linux/drivers/gpu/drm/gma500/ |
H A D | oaktrail.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (c) 2007-2011, Intel Corporation. 16 u8 hblank_hi:4; 17 u8 hactive_hi:4; 20 u8 vblank_hi:4; 21 u8 vactive_hi:4; 24 u8 vsync_pulse_width_lo:4; 25 u8 vsync_offset_lo:4; 32 u8 height_mm_hi:4; 33 u8 width_mm_hi:4; [all …]
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H A D | intel_bios.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 22 u32 aim_offset[4]; /**< from beginning of VBT */ 41 u8 rsvd3[4]; 60 #define BDB_MODE_SUPPORT_LIST 4 92 /* bits 1 */ 99 /* bits 2 */ 107 /* bits 3 */ 112 /* bits 4 */ 115 /* bits 5 */ 124 /* pre-915 */ [all …]
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H A D | oaktrail_lvds.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright © 2006-2009 Intel Corporation 24 /* The max/min PWM frequency in BPCR[31:17] - */ 26 * 15-bit field of the and then*/ 27 /* shifts to the left by one bit to get the actual 16-bit 28 * value that the 15-bits correspond to.*/ 51 dev_priv->is_lvds_on = true; in oaktrail_lvds_set_power() 52 if (dev_priv->ops->lvds_bl_power) in oaktrail_lvds_set_power() 53 dev_priv->ops->lvds_bl_power(dev, true); in oaktrail_lvds_set_power() 55 if (dev_priv->ops->lvds_bl_power) in oaktrail_lvds_set_power() [all …]
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H A D | psb_intel_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 24 # define GPIO_CLOCK_VAL_IN (1 << 4) 44 #define GMBUS_PORT_DPC 4 /* HDMIC */ 56 #define GMBUS_CYCLE_STOP (4<<25) 70 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 72 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 89 * This is the most significant 15 bits of the number of backlight cycles in a 108 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 109 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) 110 #define I915_DISPLAY_CLOCK_MASK (7 << 4) [all …]
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H A D | psb_intel_lvds.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright © 2006-2007 Intel Corporation 25 * LVDS I2C backlight control macros 70 ret = dev_priv->regs.saveBLC_PWM_CTL; in psb_intel_lvds_get_max_backlight() 72 /* Top 15bits hold the frequency mask */ in psb_intel_lvds_get_max_backlight() 78 dev_err(dev->dev, "BL bug: Reg %08x save %08X\n", in psb_intel_lvds_get_max_backlight() 79 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight() 84 * Set LVDS backlight level by I2C command 94 struct gma_i2c_chan *lvds_i2c_bus = dev_priv->lvds_i2c_bus; in psb_lvds_i2c_set_brightness() 100 .addr = lvds_i2c_bus->target_addr, in psb_lvds_i2c_set_brightness() [all …]
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/linux/drivers/gpu/drm/i915/display/ |
H A D | dvo_ch7017.c | 63 #define CH7017_DAC3_POWER_DOWN (1 << 4) 64 /** Powers down the TV out block, and DAC0-3 */ 87 /**< Low bits of horizontal active pixel input */ 90 /** High bits of horizontal active pixel input */ 92 /** High bits of vertical active line output */ 96 /**< Low bits of vertical active line output */ 99 /**< Low bits of horizontal active pixel output */ 102 /** High bits of horizontal active pixel output */ 104 /** Enables the LVDS power down state transition */ 106 /** Enables the LVDS upscaler */ [all …]
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H A D | intel_lvds_regs.h | 1 /* SPDX-License-Identifier: MIT */ 11 /* LVDS port control */ 12 #define LVDS _MMIO(0x61180) macro 14 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 15 * the DPLL semantics change when the LVDS is assigned to that pipe. 18 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 23 /* LVDS dithering flag on 965/g4x platform */ 25 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 29 /* Enable border for unscaled (or aspect-scaled) display */ 32 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per [all …]
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H A D | intel_vbt_defs.h | 2 * Copyright © 2006-2016 Intel Corporation 59 u8 hblank_hi:4; 60 u8 hactive_hi:4; 63 u8 vblank_hi:4; 64 u8 vactive_hi:4; 67 u8 vsync_pulse_width_lo:4; 68 u8 vsync_off_lo:4; 75 u8 vimage_hi:4; 76 u8 himage_hi:4; 87 * struct vbt_header - VBT Header structure [all …]
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H A D | dvo_ivch.c | 25 * Thomas Richter <thor@math.tu-berlin.de> 28 * Thomas Richter <thor@math.tu-berlin.de> 68 # define VR01_DITHER_ENABLE (1 << 4) 74 /* Enables LVDS output instead of CMOS */ 75 # define VR10_LVDS_ENABLE (1 << 4) 76 /* Enables 18-bit LVDS output. */ 78 /* Enables 24-bit LVDS or CMOS output */ 80 /* Enables 2x18-bit LVDS or CMOS output. */ 82 /* Enables 2x24-bit LVDS output */ 114 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 [all …]
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/linux/Documentation/devicetree/bindings/display/ |
H A D | xylon,logicvc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com> 16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs. 20 synthesis time. As a result, many of the device-tree bindings are meant to 24 Layers are declared in the "layers" sub-node and have dedicated configuration. 26 starting from the video memory base address for its framebuffer. In version 4, 32 - xylon,logicvc-3.02.a-display [all …]
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/linux/drivers/gpu/drm/nouveau/ |
H A D | nouveau_bios.c | 2 * Copyright 2005-2006 Erik Waling 4 * Copyright 2007-2009 Stuart Bennett 33 #include <linux/io-mapping.h> 43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 69 if (bios->major_version < 5) /* pre BIT */ in clkcmptable() 72 compare_record_len = 4; in clkcmptable() 75 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); in clkcmptable() 77 if (bios->major_version < 5) { in clkcmptable() 78 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; in clkcmptable() 79 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); in clkcmptable() [all …]
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/linux/drivers/gpu/drm/renesas/rcar-du/ |
H A D | rcar_lvds.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car LVDS Encoder 5 * Copyright (C) 2013-2018 Renesas Electronics Corporation 13 #include <linux/media-bus-format.h> 41 RCAR_LVDS_MODE_VESA = 4, 50 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */ 54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */ 59 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq); 86 static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg) in rcar_lvds_read() argument 88 return ioread32(lvds->mmio + reg); in rcar_lvds_read() [all …]
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H A D | rcar_du_drv.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * R-Car Display Unit DRM driver 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 29 #define RCAR_DU_FEATURE_CRTC_IRQ BIT(0) /* Per-CRTC IRQ */ 30 #define RCAR_DU_FEATURE_CRTC_CLOCK BIT(1) /* Per-CRTC clock */ 33 #define RCAR_DU_FEATURE_TVM_SYNC BIT(4) /* Has TV switch/sync modes */ 34 #define RCAR_DU_FEATURE_NO_BLENDING BIT(5) /* PnMR.SPIM does not have ALP nor EOR bits */ 52 * struct rcar_du_output_routing - Output routing specification 58 * of in-SoC encoder for the output. 66 * struct rcar_du_device_info - DU model-specific information [all …]
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H A D | rcar_du_drv.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * R-Car Display Unit DRM driver 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 11 #include <linux/dma-mapping.h> 32 /* ----------------------------------------------------------------------------- 45 * R8A774[34] has one RGB output and one LVDS output 57 .num_rpf = 4, 80 .num_rpf = 4, 92 * R8A77470 has two RGB outputs, one LVDS output, and 108 .num_rpf = 4, [all …]
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/linux/drivers/gpu/drm/stm/ |
H A D | lvds.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved 4 * Author(s): Raphaël GALLAIS-POU <raphael.gallais-pou@foss.st.com> for STMicroelectronics. 16 #include <linux/clk-provider.h> 19 #include <linux/media-bus-format.h> 25 /* LVDS Host registers */ 35 #define LVDS_DMLCR4 0x0024 /* data mapping lsb configuration register 4 */ 36 #define LVDS_DMMCR4 0x0028 /* data mapping msb configuration register 4 */ 46 /* LVDS Wrapper registers */ 55 #define CR_LVDSEN BIT(0) /* LVDS PHY Enable */ [all …]
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/linux/drivers/gpu/drm/bridge/ |
H A D | ti-sn65dsi83.c | 1 // SPDX-License-Identifier: GPL-2.0 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported [all …]
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H A D | lontium-lt9211.c | 1 // SPDX-License-Identifier: GPL-2.0 6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI 8 * 1xDSI -> 1xLVDS 13 #include <linux/bits.h> 17 #include <linux/media-bus-format.h> 40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */ 106 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, in lt9211_attach() 107 &ctx->bridge, flags); in lt9211_attach() 116 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid() 118 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid() [all …]
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/linux/drivers/gpu/drm/radeon/ |
H A D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 66 #define ATOM_CRTC5 4 124 #define ATOM_TV_PALM 4 134 #define ATOM_DAC1_PAL 4 179 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_… 403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_… 410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di… 475 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 [all …]
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/linux/drivers/gpu/drm/amd/include/ |
H A D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 65 #define ATOM_CRTC5 4 82 #define ATOM_PHY_PLL0 4 107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,… 133 #define ATOM_TV_PALM 4 143 #define ATOM_DAC1_PAL 4 186 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, [all …]
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/linux/drivers/gpu/drm/logicvc/ |
H A D | logicvc_of.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-2022 Bootlin 14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS }, 15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS }, 40 .name = "xylon,display-interface", 48 .name = "xylon,display-colorspace", 56 .name = "xylon,display-depth", 60 .name = "xylon,row-stride", 67 .name = "xylon,background-layer", 71 .name = "xylon,layers-configurable", [all …]
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/linux/drivers/scsi/ |
H A D | dc395x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 8 /* (SCSI chip set used Tekram ASIC TRM-S1040) */ 175 /* cmd->result */ 197 u8 ProductRev[4]; /* Product Revision */ 278 #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */ 296 /* --------- ------------- ---------------------------- */ 297 /* 07-05 0 RSVD Reversed. Always 0. */ 298 /* 04 0 OFFSET4 Reversed for LVDS. Always 0. */ 299 /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */ 304 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ [all …]
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/linux/drivers/gpu/drm/sun4i/ |
H A D | sun4i_tcon.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 6 * Boris Brezillon <boris.brezillon@free-electrons.com> 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 27 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe)) 30 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe)) 40 #define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4) 57 #define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4) 58 #define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK) 67 #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) 68 #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff) [all …]
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H A D | sun4i_tcon.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 11 #include <linux/media-bus-format.h> 48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector() 50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector() 66 return -EINVAL; in sun4i_tcon_get_pixel_depth() 68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth() 69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth() 70 return -EINVAL; in sun4i_tcon_get_pixel_depth() 72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth() [all …]
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/linux/drivers/phy/freescale/ |
H A D | phy-fsl-imx8-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0+ 9 #include <linux/clk-provider.h> 22 #include <dt-bindings/firmware/imx/rsrc.h> 29 #define CA_MASK GENMASK(4, 2) 63 ((x) < 32) ? 0xe0 | ((x) - 16) : \ 64 ((x) < 64) ? 0xc0 | ((x) - 32) : \ 65 ((x) < 128) ? 0x80 | ((x) - 64) : \ 66 ((x) - 128)) 67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f)) 68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03) [all …]
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/linux/arch/powerpc/platforms/85xx/ |
H A D | t1042rdb_diu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 20 /* DIU Pixel Clock bits of the PIXCLKCR */ 55 * LVDS also needs backlight enabled, otherwise the display in t1042rdb_set_monitor_port() 60 setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4); in t1042rdb_set_monitor_port() 84 scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg"); in t1042rdb_set_pixel_clock() 107 * range of values is 2-255. in t1042rdb_set_pixel_clock() 112 /* Disable the pixel clock, and set it to non-inverted and no delay */ in t1042rdb_set_pixel_clock() 133 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */ in t1042rdb_valid_monitor_port() 139 cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld"); in t1042rdb_diu_init()
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