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/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
16 u8 hblank_hi:4;
17 u8 hactive_hi:4;
20 u8 vblank_hi:4;
21 u8 vactive_hi:4;
24 u8 vsync_pulse_width_lo:4;
25 u8 vsync_offset_lo:4;
32 u8 height_mm_hi:4;
33 u8 width_mm_hi:4;
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H A Dintel_bios.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 u32 aim_offset[4]; /**< from beginning of VBT */
41 u8 rsvd3[4];
60 #define BDB_MODE_SUPPORT_LIST 4
92 /* bits 1 */
99 /* bits 2 */
107 /* bits 3 */
112 /* bits 4 */
115 /* bits 5 */
124 /* pre-915 */
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H A Doaktrail_lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2009 Intel Corporation
24 /* The max/min PWM frequency in BPCR[31:17] - */
26 * 15-bit field of the and then*/
27 /* shifts to the left by one bit to get the actual 16-bit
28 * value that the 15-bits correspond to.*/
51 dev_priv->is_lvds_on = true; in oaktrail_lvds_set_power()
52 if (dev_priv->ops->lvds_bl_power) in oaktrail_lvds_set_power()
53 dev_priv->ops->lvds_bl_power(dev, true); in oaktrail_lvds_set_power()
55 if (dev_priv->ops->lvds_bl_power) in oaktrail_lvds_set_power()
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H A Dpsb_intel_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 # define GPIO_CLOCK_VAL_IN (1 << 4)
44 #define GMBUS_PORT_DPC 4 /* HDMIC */
56 #define GMBUS_CYCLE_STOP (4<<25)
70 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
72 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
89 * This is the most significant 15 bits of the number of backlight cycles in a
108 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
109 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
110 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
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H A Dpsb_drv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
37 #define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
38 #define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
39 #define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
86 /* VDC registers and bits */
95 #define _PSB_DPST_PIPEB_FLAG (1<<4)
96 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
128 #define GPIO_CLOCK_VAL_IN (1 << 4)
142 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds_regs.h1 /* SPDX-License-Identifier: MIT */
11 /* LVDS port control */
12 #define LVDS _MMIO(0x61180) macro
14 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
15 * the DPLL semantics change when the LVDS is assigned to that pipe.
18 /* Selects pipe B for LVDS data. Must be set on pre-965. */
23 /* LVDS dithering flag on 965/g4x platform */
25 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
29 /* Enable border for unscaled (or aspect-scaled) display */
32 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
26 starting from the video memory base address for its framebuffer. In version 4,
32 - xylon,logicvc-3.02.a-display
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bios.c2 * Copyright 2005-2006 Erik Waling
4 * Copyright 2007-2009 Stuart Bennett
33 #include <linux/io-mapping.h>
43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
69 if (bios->major_version < 5) /* pre BIT */ in clkcmptable()
72 compare_record_len = 4; in clkcmptable()
75 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); in clkcmptable()
77 if (bios->major_version < 5) { in clkcmptable()
78 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; in clkcmptable()
79 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); in clkcmptable()
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_drv.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
29 #define RCAR_DU_FEATURE_CRTC_IRQ BIT(0) /* Per-CRTC IRQ */
30 #define RCAR_DU_FEATURE_CRTC_CLOCK BIT(1) /* Per-CRTC clock */
33 #define RCAR_DU_FEATURE_TVM_SYNC BIT(4) /* Has TV switch/sync modes */
34 #define RCAR_DU_FEATURE_NO_BLENDING BIT(5) /* PnMR.SPIM does not have ALP nor EOR bits */
52 * struct rcar_du_output_routing - Output routing specification
58 * of in-SoC encoder for the output.
66 * struct rcar_du_device_info - DU model-specific information
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H A Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
32 /* -----------------------------------------------------------------------------
45 * R8A774[34] has one RGB output and one LVDS output
57 .num_rpf = 4,
80 .num_rpf = 4,
92 * R8A77470 has two RGB outputs, one LVDS output, and
108 .num_rpf = 4,
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H A Drcar_du_group.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Channels Pair
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
23 * counterpart in the DU documentation, that models those semi-global resources.
35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); in rcar_du_group_read()
40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); in rcar_du_group_write()
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
66 #define ATOM_CRTC5 4
124 #define ATOM_TV_PALM 4
134 #define ATOM_DAC1_PAL 4
179 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
475 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
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H A Dradeon_atombios.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
51 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ in radeon_lookup_i2c_gpio_quirks()
52 if ((rdev->family == CHIP_R420) || in radeon_lookup_i2c_gpio_quirks()
53 (rdev->family == CHIP_R423) || in radeon_lookup_i2c_gpio_quirks()
54 (rdev->family == CHIP_RV410)) { in radeon_lookup_i2c_gpio_quirks()
55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || in radeon_lookup_i2c_gpio_quirks()
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || in radeon_lookup_i2c_gpio_quirks()
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { in radeon_lookup_i2c_gpio_quirks()
58 gpio->ucClkMaskShift = 0x19; in radeon_lookup_i2c_gpio_quirks()
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
65 #define ATOM_CRTC5 4
82 #define ATOM_PHY_PLL0 4
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
133 #define ATOM_TV_PALM 4
143 #define ATOM_DAC1_PAL 4
186 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
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/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
71 .name = "xylon,layers-configurable",
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/linux/drivers/scsi/
H A Ddc395x.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 /* (SCSI chip set used Tekram ASIC TRM-S1040) */
175 /* cmd->result */
197 u8 ProductRev[4]; /* Product Revision */
278 #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
296 /* --------- ------------- ---------------------------- */
297 /* 07-05 0 RSVD Reversed. Always 0. */
298 /* 04 0 OFFSET4 Reversed for LVDS. Always 0. */
299 /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */
304 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
27 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe))
30 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe))
40 #define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4)
57 #define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4)
58 #define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
67 #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
68 #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff)
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H A Dsun4i_tcon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
29 #define CA_MASK GENMASK(4, 2)
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
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/linux/arch/powerpc/platforms/85xx/
H A Dt1042rdb_diu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 /* DIU Pixel Clock bits of the PIXCLKCR */
55 * LVDS also needs backlight enabled, otherwise the display in t1042rdb_set_monitor_port()
60 setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4); in t1042rdb_set_monitor_port()
84 scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg"); in t1042rdb_set_pixel_clock()
107 * range of values is 2-255. in t1042rdb_set_pixel_clock()
112 /* Disable the pixel clock, and set it to non-inverted and no delay */ in t1042rdb_set_pixel_clock()
133 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */ in t1042rdb_valid_monitor_port()
139 cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld"); in t1042rdb_diu_init()
H A Dp1022_ds.c42 * Board-specific initialization of the DIU. This code should probably be
51 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
77 * Note that we need to byte-swap the value before it's written to the AD
99 #define AD_COMP_1_SHIFT 4
132 * The localbus BRx registers only store the lower 32 bits of the address. To
133 * obtain the upper four bits, we need to scan the LAW table. The entry which
134 * maps to the localbus will contain the upper four bits.
140 * If we only have 32-bit addressing, then the BRx address *is* the in lbc_br_to_phys()
153 /* Extract the upper four bits */ in lbc_br_to_phys()
181 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); in p1022ds_set_monitor_port()
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
36 fsl,dc-stream-id:
52 "^port@[1-4]$":
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_link_encoder.c36 enc10->base.ctx
38 enc10->base.ctx->logger
41 (enc10->link_regs->reg)
45 enc10->link_shift->field_name, enc10->link_mask->field_name
48 (enc10->link_regs->index)
100 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; in dcn30_link_encoder_construct()
102 struct dcn10_link_encoder *enc10 = &enc20->enc10; in dcn30_link_encoder_construct()
104 enc10->base.funcs = &dcn30_link_enc_funcs; in dcn30_link_encoder_construct()
105 enc10->base.ctx = init_data->ctx; in dcn30_link_encoder_construct()
106 enc10->base.id = init_data->encoder; in dcn30_link_encoder_construct()
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 enc110->base.ctx
59 enc110->base.ctx->logger
62 (enc110->link_regs->reg)
65 (enc110->aux_regs->reg)
68 (enc110->hpd_regs->reg)
75 * ASIC-dependent, actual values for register programming
91 (reg + enc110->offsets.dig)
94 (reg + enc110->offsets.dp)
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
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