Lines Matching +full:lvds +full:- +full:4 +full:bits

63 #define CH7017_DAC3_POWER_DOWN		(1 << 4)
64 /** Powers down the TV out block, and DAC0-3 */
87 /**< Low bits of horizontal active pixel input */
90 /** High bits of horizontal active pixel input */
92 /** High bits of vertical active line output */
96 /**< Low bits of vertical active line output */
99 /**< Low bits of horizontal active pixel output */
102 /** High bits of horizontal active pixel output */
104 /** Enables the LVDS power down state transition */
106 /** Enables the LVDS upscaler */
113 #define CH7017_LVDS_DUAL_CHANNEL_EN	(1 << 4)
119 /** Enables the LVDS panel output path */
121 /** Enables the LVDS panel backlight */
134 # define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4
140 # define CH7017_LVDS_PLL_VCO_SHIFT	4
147 # define CH7017_LVDS_CHANNEL_B		(1 << 4)
173 			.addr = dvo->target_addr,
179 			.addr = dvo->target_addr,
185 	return i2c_transfer(dvo->i2c_bus, msgs, 2) == 2;
192 		.addr = dvo->target_addr,
197 	return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1;
212 	dvo->i2c_bus = adapter;
213 	dvo->dev_priv = priv;
231 			      val, adapter->name, dvo->target_addr);
236 		      str, adapter->name, dvo->target_addr);
252 	if (mode->clock > 160000)
271 	/* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
272 	if (mode->clock < 100000) {
302 	horizontal_active_pixel_input = mode->hdisplay & 0x00ff;
304 	vertical_active_line_output = mode->vdisplay & 0x00ff;
305 	horizontal_active_pixel_output = mode->hdisplay & 0x00ff;
307 	active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) |
308 				   (((mode->vdisplay & 0x0700) >> 8) << 3);
311 			  (mode->hdisplay & 0x0700) >> 8;
327 	/* Turn the LVDS back on with new settings. */
350 		/* Turn on the LVDS */
354 		/* Turn off the LVDS */
398 	struct ch7017_priv *priv = dvo->dev_priv;
402 		dvo->dev_priv = NULL;