Lines Matching +full:lvds +full:- +full:4 +full:bits
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
66 #define ATOM_CRTC5 4
124 #define ATOM_TV_PALM 4
134 #define ATOM_DAC1_PAL 4
179 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
475 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
705 // =1: LVDS encoder
708 // =4: SDVO encoder
740 #define ATOM_ENCODER_MODE_SDVO 4
774 // =1: LVDS encoder
777 // =4: SDVO encoder
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
820 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
826 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
850 // =1: LVDS encoder
853 // =4: SDVO encoder
866 //ucTableContentRevision=4
868 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
873 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
879 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
909 // =1: LVDS encoder
912 // =4: SDVO encoder
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
957 // [0]=0: 4 lane Link,
965 // [5:4]PCIE lane Sel
967 // =1: lane 4~7
972 UCHAR ucReserved[4];
1010 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
1086 UCHAR ucReserved[4];
1095 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1107 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1146 // Bit5:4
1160 // Structures used by UNIPHYTransmitterControlTable V1.4
1163 // ucTableContentRevision=4
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1191 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1203 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1241 // Bit5:4
1273 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= p…
1274 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1294 #define ATOM_PHY_ID_UNIPHYE 4
1312 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1339 // Bit6:4
1532 //#define ATOM_ENCODER_MODE_SDVO 4
1560 #define MISC_DEVICE_INDEX_SHIFT 4
1573 …UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device i…
1604 // V1.4 for RoadRunner
1626 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1652 // bit[4]= RefClock source for PPLL.
1654 // =1: other external clock source, which is pre-defined
1675 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1678 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1700 // bit[4]= RefClock source for PPLL.
1702 …// =1: other external clock source, which is pre-defined …
1716 …DMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
1761 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1775 … DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
1777 …ISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
1783 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1784 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1830 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1847 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
1897 /****************************LVDS SS Command Table Definitions**********************/
1906 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1941 // Bits[7:4] reserved
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
1966 // Bits[7:4] reserved
2007 /****************************LVDS and other encoder command table definitions *********************…
2055 // =1: Gray level 4
2132 UCHAR ucReseved[4];
2149 // bit1=0: non-coherent mode
2201 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2228 // used by both SetVoltageTable v1.3 and v1.4
2240 #define VOLTAGE_TYPE_VDDCI 4
2245 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID re…
2247 …VEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
2248 …_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
2380 …SIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2404 …o; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2416 …UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and vid…
2417 …UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and …
2419 …; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio …
2420 …scInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Conf…
2421 …AR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2427 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2443 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk S…
2444 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk S…
2464 USHORT HyperMemory_Size:4;
2484 USHORT HyperMemory_Size:4;
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2764 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2771 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is re…
2781 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2795 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max …
2796 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min …
2798 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value…
2799 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the valu…
2801 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the ma…
2802 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min…
2833 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
2857 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2867 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
2873 Bit[4]=1: CLMC is supported and enabled on current system.
2886 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2889 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
2892 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
2893 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
2896 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
2898 [15:8] - Lane configuration attribute;
2899 [23:16]- Connector type, possible value:
2905 [31:24]- Reserved
2913 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
2917 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
2927 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2939 … if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
2940 … if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
2941 … if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
2942 …if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (…
2955 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2960 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
2991 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This re…
3002 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3010 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3015 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3016 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3019 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3153 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3162 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3172 // [7:0] - I2C LINE Associate ID
3173 // = 0 - no I2C
3174 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3176 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3178 // = 3-7 Reserved for future I2C engines
3179 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3186 UCHAR bfI2C_LineMux:4;
3188 UCHAR bfI2C_LineMux:4;
3284 // usModeMiscInfo-
3296 //usRefreshRate-
3467 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
3472 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3476 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3477 //Bit 6 5 4
3478 // 0 0 0 - Color bit depth is undefined
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3512 … // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3522 … // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3523 // Bit7-3: Reserved
3559 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3560 //Bit 6 5 4
3561 // 0 0 0 - Color bit depth is undefined
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3576 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
3581 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3585 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3586 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
3612 #define LCD_MODE_CAP_PANEL_OFF 4
3631 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
3665 #define EXEC_SS_DELAY_SHIFT 4
3666 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
3682 //ATOM_TV_PALM 4
3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3740 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAG…
3741 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3754 …(ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3755 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
3812 … ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0x…
3826 // ucTableFormatRevision=1,ucTableContentRevision=4, the structure remains
3835 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3839 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3841 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3885 //ucGPIO_ID pre-define id for multiple usage
3907 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
3928 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
3932 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Lette…
3933 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Lette…
3937 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
3938 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
3947 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, whic…
3967 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3984 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4052 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to…
4074 #define EXT_HPDPIN_LUTINDEX_4 4
4084 #define EXT_AUXDDC_LUTINDEX_4 4
4091 //for DP connector, eDP, DP to VGA/LVDS
4094 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: fro…
4114 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
4180 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
4288 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4316 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
4341 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4347 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4436 #define CONNECTOR_TYPE_HDMI 4
4480 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4573 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
4574 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
4575 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
4576 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
4578 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4579 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4580 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4638 // 4:2 – load line slope trim.
4795 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
4864 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
4889 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
4890 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4892 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4895 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4898 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
4909 Bit[1]=0: DDR-DLL shut-down feature disabled.
4910 1: DDR-DLL shut-down feature enabled.
4911 Bit[2]=0: DDR-PLL Power down feature disabled.
4912 … 1: DDR-PLL Power down feature enabled.
4918 … supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4924 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4931 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4937 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit…
4938 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit …
4943 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
4944 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
4945 …[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower l…
4946 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
4947 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
4993 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5048 ULONG ulNbpStateMemclkFreq[4];
5051 ULONG ulNbpStateNClkFreq[4];
5079 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5093 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b )…
5094 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
5095 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5096 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
5097 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
5098 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
5113 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5114 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5116 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5119 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5122 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5133 Bit[1]=0: DDR-DLL shut-down feature disabled.
5134 1: DDR-DLL shut-down feature enabled.
5135 Bit[2]=0: DDR-PLL Power down feature disabled.
5136 … 1: DDR-PLL Power down feature enabled.
5144 … supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5150 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5157 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5163 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit…
5164 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit …
5169 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
5170 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5171 …[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower l…
5172 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5173 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
5175 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
5178 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON…
5179 …ean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->…
5181 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( …
5182 …n use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->…
5185 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from dat…
5186 … VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY…
5189 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from var…
5190 … use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY…
5193 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIG…
5198 …LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal activ…
5203 …LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal of…
5209 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
5220 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5269 ULONG ulNbpStateMemclkFreq[4];
5271 ULONG ulNbpStateNClkFreq[4];
5272 USHORT usNBPStateVoltage[4];
5280 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5283 sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4…
5296 … bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
5297 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
5298 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5299 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
5300 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
5301 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
5308 bit[4]=0: Disable DFS bypass feature
5314 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5315 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5317 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5320 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5323 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5333 Bit[1]=0: DDR-DLL shut-down feature disabled.
5334 1: DDR-DLL shut-down feature enabled.
5335 Bit[2]=0: DDR-PLL Power down feature disabled.
5336 1: DDR-PLL Power down feature enabled.
5342 … supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5349 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
5357 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
5363 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit…
5364 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit …
5370 … Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS opti…
5371 ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory.
5372 ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory.
5374 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
5375 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5376 …[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower l…
5377 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5378 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
5380 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
5384 …LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable sig…
5385 …ean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->…
5388 …LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brig…
5389 …n use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->…
5392 …LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCD…
5393 … VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY…
5396 …LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_…
5397 … use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY…
5400 …LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal act…
5404 …LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal activ…
5409 …LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal of…
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5417 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
5418 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
5419 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
5485 #define ASIC_INTERNAL_SS_ON_TMDS 4
5498 … //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5517 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
5529 … //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5554 #define ATOM_LCD_INFO_DEF 4
5612 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
5885 #define ATOM_S6_ACC_MODE_SHIFT 4
5981 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
5983 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
5984 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
5988 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
5989 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
6156 #define HDP4_INTERRUPT_ID 4
6182 #define INDIRECT_IO_PCIEP 4
6369 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
6398 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6400 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6406 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
6407 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6408 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6425 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6427 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6433 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
6434 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6435 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6557 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6563 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
6567 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
6582 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6603 …CHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5…
6605 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6608 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6611 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6613 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6645 …CHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5…
6647 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6650 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6653 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6655 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6664 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6676 …CHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5…
6678 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6681 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6684 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6686 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6695 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6714 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6715 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6716 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6722 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
6725 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6758 …MemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0]…
6759 UCHAR ucReservde[4];
6821 #define SW_I2C_IO_START 4
6833 #define SW_I2C_CNTL_OPEN 4
6857 UCHAR VbeSignature[4];
6860 UCHAR Capabilities[4];
6921 UCHAR BitsPerPixel; // db ? ; bits per pixel
6929 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
6931 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
6933 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
6935 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
6941 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6942 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
7142 … //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
7291 #define SELECT_DCIO_IMPCAL 4
7299 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7300 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7301 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7308 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7309 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7310 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7432 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7437 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7442 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7450 // [7:4] - connector type
7451 // = 1 - VGA connector
7452 // = 2 - DVI-I
7453 // = 3 - DVI-D
7454 // = 4 - DVI-A
7455 // = 5 - SVIDEO
7456 // = 6 - COMPOSITE
7457 // = 7 - LVDS
7458 // = 8 - DIGITAL LINK
7459 // = 9 - SCART
7460 // = 0xA - HDMI_type A
7461 // = 0xB - HDMI_type B
7462 // = 0xE - Special case1 (DVI+DIN)
7464 // [3:0] - DAC Associated
7465 // = 0 - no DAC
7466 // = 1 - DACA
7467 // = 2 - DACB
7468 // = 3 - External DAC
7475 UCHAR bfConnectorType:4;
7476 UCHAR bfAssociatedDAC:4;
7478 UCHAR bfAssociatedDAC:4;
7479 UCHAR bfConnectorType:4;
7533 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7540 #define ATOM_MAX_MISC_INFO 4
7643 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
7653 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
7663 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …
7949 ULONG Reserved[4]; //0x3C