Lines Matching +full:lvds +full:- +full:4 +full:bits
1 /* SPDX-License-Identifier: GPL-2.0-only */
24 # define GPIO_CLOCK_VAL_IN (1 << 4)
44 #define GMBUS_PORT_DPC 4 /* HDMIC */
56 #define GMBUS_CYCLE_STOP (4<<25)
70 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
72 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
89 * This is the most significant 15 bits of the number of backlight cycles in a
108 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
109 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
110 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
155 * - PLL enabled
156 * - pipe enabled
157 * - LVDS/DVOB/DVOC on
250 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
256 * in DVO non-gang */
268 * digital display port. The range is 4 to 13; 10 or more
280 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
351 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
385 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
386 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
413 * Programmed value is multiplier - 1, up to 5x.
426 /* Bits to be preserved when writing */
431 * This register controls the LVDS output enable, pipe selection, and data
436 #define LVDS 0x61180 macro
438 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
439 * the DPLL semantics change when the LVDS is assigned to that pipe.
442 /* Selects pipe B for LVDS data. Must be set on pre-965. */
449 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
467 #define LVDS_CLKB_POWER_MASK (3 << 4)
468 #define LVDS_CLKB_POWER_DOWN (0 << 4)
469 #define LVDS_CLKB_POWER_UP (3 << 4)
471 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
472 * setting for whether we are in dual-channel mode. The B3 pair will
619 #define DISPPLANE_BOTTOM (4)
776 /* #define LVDS 0x61180 */
833 #define RX_LP_TX_SYNC_ERROR (1 << 4)
905 #define DPI_BACK_LIGHT_ON (1 << 4)
995 * The display module returns the self-diagnostic results following
1025 * No status bits are changed.
1031 * No status bits are changed.
1042 No status bits are changed.
1048 No status bits are changed.
1055 * No status bits are changed.
1062 * No status bits are changed.
1094 * to display modules frame memory,bits B[7:5] and B3, and from the
1095 * display modules frame memory to the display device, bits B[2:0] and B4.
1121 * Bits D[6:4] DPI Pixel Format Definition
1122 * Bits D[2:0] DBI Pixel Format Definition
1123 * Bits D7 and D3 are not used.
1188 #define AMBIENT_LIGHT_SENSE_ON (1 << 4)
1237 #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
1241 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
1253 # define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4)
1254 # define SB_BYTE_ENABLE_SHIFT 4
1268 /* 32-bit value read/written from the DPIO reg. */
1270 /* 32-bit address of the DPIO reg to be read/written. */
1316 #define SB_P2_14 2 /* LVDS single */
1317 #define SB_P2_7 3 /* LVDS double */
1337 /* Link training mode - select a suitable mode for each stage */
1353 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1388 #define DP_SYNC_VS_HIGH (1 << 4)
1452 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1470 * Attributes and VB-ID.