Lines Matching +full:lvds +full:- +full:4 +full:bits
1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
13 #include <linux/media-bus-format.h>
41 RCAR_LVDS_MODE_VESA = 4,
50 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
59 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
86 static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
88 return ioread32(lvds->mmio + reg);
91 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
93 iowrite32(data, lvds->mmio + reg);
96 /* -----------------------------------------------------------------------------
100 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
113 rcar_lvds_write(lvds, LVDPLLCR, val);
116 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
129 rcar_lvds_write(lvds, LVDPLLCR, val);
141 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
157 * The LVDS PLL is made of a pre-divider and a multiplier (strangely
158 * enough called M and N respectively), followed by a post-divider E.
160 * ,-----. ,-----. ,-----. ,-----.
161 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
162 * `-----' ,-> | | `-----' | `-----'
163 * | `-----' |
164 * | ,-----. |
165 * `-------- | 1/N | <-------'
166 * `-----'
171 * clock (as LVDS transmits 7 bits per lane per clock sample).
173 * ,-------. ,-----. |\
174 * Fout --> | 1/DIV | --> | 1/7 | --> | |
175 * `-------' | `-----' | | --> dot clock
176 * `------------> | |
179 * The /7 divider is optional, it is enabled when the LVDS PLL is used
180 * to drive the LVDS encoder, and disabled when used to generate a dot
181 * clock for the DU RGB output, without using the LVDS encoder.
192 * allowed values for the pre-divider M (normal range 1-8).
208 * 60-120).
224 * post-divider E (normal value 1, 2 or 4).
243 diff = abs(fout / div - target);
245 if (diff < pll->diff) {
246 pll->diff = diff;
247 pll->pll_m = m;
248 pll->pll_n = n;
249 pll->pll_e = e;
250 pll->div = div;
251 pll->clksel = clksel;
261 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
262 / div7 / pll->div;
263 error = (long)(output - target) * 10000 / (long)target;
265 dev_dbg(lvds->dev,
266 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
268 error < 0 ? -error % 100 : error % 100,
269 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
272 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
275 struct pll_info pll = { .diff = (unsigned long)-1 };
278 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
280 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
282 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
286 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
290 | LVDPLLCR_PLLE(pll.pll_e - 1);
295 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
302 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
303 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
305 rcar_lvds_write(lvds, LVDDIV, 0);
308 /* -----------------------------------------------------------------------------
312 static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds,
319 * There is no API yet to retrieve LVDS mode from a bridge, only panels
322 if (!lvds->panel)
325 info = &connector->display_info;
326 if (!info->num_bus_formats || !info->bus_formats) {
327 dev_warn(lvds->dev,
328 "no LVDS bus format reported, using JEIDA\n");
332 switch (info->bus_formats[0]) {
341 dev_warn(lvds->dev,
342 "unsupported LVDS bus format 0x%04x, using JEIDA\n",
343 info->bus_formats[0]);
347 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
358 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
363 ret = pm_runtime_resume_and_get(lvds->dev);
367 /* Enable the companion LVDS encoder in dual-link mode. */
368 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
369 rcar_lvds_enable(lvds->companion, state, crtc, connector);
374 * HSYNC -> CTRL0
375 * VSYNC -> CTRL1
376 * DISP -> CTRL2
377 * 0 -> CTRL3
379 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
383 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
390 rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
392 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
395 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK) {
403 bool swap_pixels = lvds->link_type ==
408 * an LVDS dual-link connection.
414 | (lvds->companion && swap_pixels ?
417 rcar_lvds_write(lvds, LVDSTRIPE, lvdstripe);
422 * dual-link mode.
427 if ((lvds->link_type == RCAR_LVDS_SINGLE_LINK || lvds->companion) &&
428 !(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
432 &crtc_state->adjusted_mode;
434 lvds->info->pll_setup(lvds, mode->clock * 1000);
437 /* Set the LVDS mode and select the input. */
438 lvdcr0 = rcar_lvds_get_lvds_mode(lvds, connector) << LVDCR0_LVMD_SHIFT;
440 if (lvds->bridge.encoder) {
445 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
448 rcar_lvds_write(lvds, LVDCR1,
452 if (lvds->info->gen < 3) {
453 /* Enable LVDS operation and turn the bias circuitry on. */
455 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
458 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
464 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
467 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
468 /* Set LVDS normal mode. */
470 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
473 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
475 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
479 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
480 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
483 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
490 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
495 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
499 * Clear the LVDCR0 bits in the order specified by the hardware
501 * clear all remaining bits.
503 lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
506 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
508 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
510 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
513 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
515 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
518 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
520 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
523 rcar_lvds_write(lvds, LVDCR0, 0);
524 rcar_lvds_write(lvds, LVDCR1, 0);
527 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
528 rcar_lvds_write(lvds, LVDPLLCR, 0);
530 /* Disable the companion LVDS encoder in dual-link mode. */
531 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
532 rcar_lvds_disable(lvds->companion);
534 pm_runtime_put_sync(lvds->dev);
537 /* -----------------------------------------------------------------------------
538 * Clock - D3/E3 only
544 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
547 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
548 return -ENODEV;
550 dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
552 ret = pm_runtime_resume_and_get(lvds->dev);
556 rcar_lvds_pll_setup_d3_e3(lvds, freq, dot_clk_only);
564 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
566 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
569 dev_dbg(lvds->dev, "disabling LVDS PLL\n");
574 rcar_lvds_write(lvds, LVDPLLCR, 0);
576 pm_runtime_put_sync(lvds->dev);
580 /* -----------------------------------------------------------------------------
591 bridge->encoder);
592 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
600 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
603 * For D3 and E3, disabling the LVDS encoder before the DU would stall
609 * We could clear the LVRES bit already to disable the LVDS output, but
612 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
622 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
626 * The internal LVDS encoder has a restricted clock frequency operating
630 min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
631 adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
639 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
641 if (!lvds->next_bridge)
644 return drm_bridge_attach(bridge->encoder, lvds->next_bridge, bridge,
660 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
662 return lvds->link_type != RCAR_LVDS_SINGLE_LINK;
668 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
670 return lvds->next_bridge != NULL;
674 /* -----------------------------------------------------------------------------
678 static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
684 struct device *dev = lvds->dev;
688 /* Locate the companion LVDS encoder for dual-link operation, if any. */
689 companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
697 match = of_match_device(dev->driver->of_match_table, dev);
698 if (!of_device_is_compatible(companion, match->compatible)) {
699 dev_err(dev, "Companion LVDS encoder is invalid\n");
700 ret = -ENXIO;
706 * dual-link mode. We do this by looking at the DT port nodes we are
710 port0 = of_graph_get_port_by_id(dev->of_node, 1);
718 lvds->link_type = RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
721 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
725 * Early dual-link bridge specific implementations populate the
730 if (lvds->next_bridge->timings &&
731 lvds->next_bridge->timings->dual_link)
732 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
734 lvds->link_type = RCAR_LVDS_SINGLE_LINK;
737 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK) {
738 dev_dbg(dev, "Single-link configuration detected\n");
742 lvds->companion = of_drm_find_bridge(companion);
743 if (!lvds->companion) {
744 ret = -EPROBE_DEFER;
749 "Dual-link configuration detected (companion encoder %pOF)\n",
752 if (lvds->link_type == RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
764 companion_lvds = bridge_to_rcar_lvds(lvds->companion);
765 companion_lvds->link_type = lvds->link_type;
773 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
777 ret = drm_of_find_panel_or_bridge(lvds->dev->of_node, 1, 0,
778 &lvds->panel, &lvds->next_bridge);
782 if (lvds->panel) {
783 lvds->next_bridge = devm_drm_panel_bridge_add(lvds->dev,
784 lvds->panel);
785 if (IS_ERR_OR_NULL(lvds->next_bridge)) {
786 ret = -EINVAL;
791 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
792 ret = rcar_lvds_parse_dt_companion(lvds);
796 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
797 * used for the DPAD output even when the LVDS output is not connected.
801 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
802 return ret == -ENODEV ? 0 : ret;
807 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
812 clk = devm_clk_get(lvds->dev, name);
816 if (PTR_ERR(clk) == -ENOENT && optional)
819 dev_err_probe(lvds->dev, PTR_ERR(clk), "failed to get %s clock\n",
825 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
827 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
828 if (IS_ERR(lvds->clocks.mod))
829 return PTR_ERR(lvds->clocks.mod);
832 * LVDS encoders without an extended PLL have no external clock inputs.
834 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
837 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
838 if (IS_ERR(lvds->clocks.extal))
839 return PTR_ERR(lvds->clocks.extal);
841 lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
842 if (IS_ERR(lvds->clocks.dotclkin[0]))
843 return PTR_ERR(lvds->clocks.dotclkin[0]);
845 lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
846 if (IS_ERR(lvds->clocks.dotclkin[1]))
847 return PTR_ERR(lvds->clocks.dotclkin[1]);
850 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
851 !lvds->clocks.dotclkin[1]) {
852 dev_err(lvds->dev,
854 return -EINVAL;
877 struct rcar_lvds *lvds;
880 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
881 if (lvds == NULL)
882 return -ENOMEM;
884 platform_set_drvdata(pdev, lvds);
886 lvds->dev = &pdev->dev;
887 lvds->info = of_device_get_match_data(&pdev->dev);
891 lvds->info = attr->data;
893 ret = rcar_lvds_parse_dt(lvds);
897 lvds->bridge.funcs = &rcar_lvds_bridge_ops;
898 lvds->bridge.of_node = pdev->dev.of_node;
900 lvds->mmio = devm_platform_ioremap_resource(pdev, 0);
901 if (IS_ERR(lvds->mmio))
902 return PTR_ERR(lvds->mmio);
904 ret = rcar_lvds_get_clocks(lvds);
908 lvds->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
909 if (IS_ERR(lvds->rstc))
910 return dev_err_probe(&pdev->dev, PTR_ERR(lvds->rstc),
913 pm_runtime_enable(&pdev->dev);
915 drm_bridge_add(&lvds->bridge);
922 struct rcar_lvds *lvds = platform_get_drvdata(pdev);
924 drm_bridge_remove(&lvds->bridge);
926 pm_runtime_disable(&pdev->dev);
959 { .compatible = "renesas,r8a7742-lvds", .data = &rcar_lvds_gen2_info },
960 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
961 { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
962 { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
963 { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
964 { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
965 { .compatible = "renesas,r8a774e1-lvds", .data = &rcar_lvds_gen3_info },
966 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info },
967 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
968 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
969 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
970 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
971 { .compatible = "renesas,r8a77961-lvds", .data = &rcar_lvds_gen3_info },
972 { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
973 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
974 { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
975 { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
976 { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
984 struct rcar_lvds *lvds = dev_get_drvdata(dev);
986 clk_disable_unprepare(lvds->clocks.mod);
988 reset_control_assert(lvds->rstc);
995 struct rcar_lvds *lvds = dev_get_drvdata(dev);
998 ret = reset_control_deassert(lvds->rstc);
1002 ret = clk_prepare_enable(lvds->clocks.mod);
1009 reset_control_assert(lvds->rstc);
1022 .name = "rcar-lvds",
1031 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");