Lines Matching +full:lvds +full:- +full:4 +full:bits
1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
13 #include <linux/bits.h>
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
106 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
107 &ctx->bridge, flags);
116 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3);
118 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret);
125 dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n",
127 return -EINVAL;
148 return regmap_multi_reg_write(ctx->regmap, lt9211_system_init_seq,
173 /* 0x8588: BIT 6 set = MIPI-RX, BIT 4 unset = LVDS-TX */
176 { REG_DSI_LANE, REG_DSI_LANE_COUNT(ctx->dsi->lanes) },
192 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_phy_seq,
197 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_cal_reset_seq,
202 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_dig_seq,
207 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_div_reset_seq,
214 return regmap_multi_reg_write(ctx->regmap, lt9211_rx_div_clear_seq,
229 ret = regmap_write(ctx->regmap, 0x8600, 0x01);
237 ret = regmap_bulk_read(ctx->regmap, 0x8608, bc, sizeof(bc));
244 /* Width/Height/Format Auto-detection */
245 ret = regmap_bulk_read(ctx->regmap, 0xd082, buf, sizeof(buf));
250 height = (buf[3] << 8) | buf[4];
258 dev_err(ctx->dev, "Unsupported DSI pixel format 0x%01x\n",
260 return -EINVAL;
263 if (width != mode->hdisplay) {
264 dev_err(ctx->dev,
266 width, mode->hdisplay);
267 return -EINVAL;
270 if (height != mode->vdisplay) {
271 dev_err(ctx->dev,
273 height, mode->vdisplay);
274 return -EINVAL;
277 dev_dbg(ctx->dev, "RX: %dx%d format=0x%01x byteclock=%d kHz\n",
287 { 0xd00d, (mode->vtotal >> 8) & 0xff },
288 { 0xd00e, mode->vtotal & 0xff },
289 { 0xd00f, (mode->vdisplay >> 8) & 0xff },
290 { 0xd010, mode->vdisplay & 0xff },
291 { 0xd011, (mode->htotal >> 8) & 0xff },
292 { 0xd012, mode->htotal & 0xff },
293 { 0xd013, (mode->hdisplay >> 8) & 0xff },
294 { 0xd014, mode->hdisplay & 0xff },
295 { 0xd015, (mode->vsync_end - mode->vsync_start) & 0xff },
296 { 0xd016, (mode->hsync_end - mode->hsync_start) & 0xff },
297 { 0xd017, ((mode->vsync_start - mode->vdisplay) >> 8) & 0xff },
298 { 0xd018, (mode->vsync_start - mode->vdisplay) & 0xff },
299 { 0xd019, ((mode->hsync_start - mode->hdisplay) >> 8) & 0xff },
300 { 0xd01a, (mode->hsync_start - mode->hdisplay) & 0xff },
303 return regmap_multi_reg_write(ctx->regmap, lt9211_timing,
331 ret = regmap_write(ctx->regmap, 0x822d, 0x48);
335 if (mode->clock < 44000) {
336 ret = regmap_write(ctx->regmap, 0x8235, 0x83);
337 } else if (mode->clock < 88000) {
338 ret = regmap_write(ctx->regmap, 0x8235, 0x82);
339 } else if (mode->clock < 176000) {
340 ret = regmap_write(ctx->regmap, 0x8235, 0x81);
342 dev_err(ctx->dev,
344 mode->clock);
345 return -EINVAL;
354 ret = regmap_multi_reg_write(ctx->regmap, lt9211_pcr_seq,
360 ret = regmap_read_poll_timeout(ctx->regmap, 0xd087, pval, pval & 0x8,
363 dev_err(ctx->dev, "PCR unstable, ret=%i\n", ret);
374 /* BIT(7) is LVDS dual-port */
375 { 0x823b, 0x38 | (ctx->lvds_dual_link ? BIT(7) : 0) },
389 /* LVDS channel order, Odd:Even 0x10..A:B, 0x40..B:A */
390 { 0x8646, ctx->lvds_dual_link_even_odd_swap ? 0x40 : 0x10 },
397 (de ? BIT(5) : 0) | (bpp24 ? BIT(4) : 0) },
400 { 0x855c, ctx->lvds_dual_link ? BIT(0) : 0 },
413 { 0x8237, ctx->lvds_dual_link ? 0x2a : 0x29 },
425 ret = regmap_multi_reg_write(ctx->regmap, system_lt9211_tx_phy_seq,
430 ret = regmap_multi_reg_write(ctx->regmap, system_lt9211_tx_dig_seq,
435 ret = regmap_multi_reg_write(ctx->regmap, system_lt9211_tx_pll_seq,
440 ret = regmap_read_poll_timeout(ctx->regmap, 0x871f, pval, pval & 0x80,
443 dev_err(ctx->dev, "TX PLL unstable, ret=%i\n", ret);
447 ret = regmap_read_poll_timeout(ctx->regmap, 0x8720, pval, pval & 0x80,
450 dev_err(ctx->dev, "TX PLL unstable, ret=%i\n", ret);
471 ret = regulator_enable(ctx->vccio);
473 dev_err(ctx->dev, "Failed to enable vccio: %d\n", ret);
478 gpiod_set_value(ctx->reset_gpio, 1);
479 usleep_range(20000, 21000); /* Very long post-reset delay. */
481 /* Get the LVDS format from the bridge state. */
483 bus_flags = bridge_state->output_bus_cfg.flags;
485 switch (bridge_state->output_bus_cfg.format) {
501 * LVDS bus pixel format, use SPWG24 default
506 dev_warn(ctx->dev,
507 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
508 bridge_state->output_bus_cfg.format);
517 bridge->encoder);
518 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
520 mode = &crtc_state->adjusted_mode;
551 dev_dbg(ctx->dev, "LT9211 enabled.\n");
564 gpiod_set_value(ctx->reset_gpio, 0);
567 ret = regulator_disable(ctx->vccio);
569 dev_err(ctx->dev, "Failed to disable vccio: %d\n", ret);
571 regcache_mark_dirty(ctx->regmap);
579 /* LVDS output clock range 25..176 MHz */
580 if (mode->clock < 25000)
582 if (mode->clock > 176000)
607 /* This is the DSI-end bus format */
629 struct device *dev = ctx->dev;
634 ctx->vccio = devm_regulator_get(dev, "vccio");
635 if (IS_ERR(ctx->vccio))
636 return dev_err_probe(dev, PTR_ERR(ctx->vccio),
639 ctx->lvds_dual_link = false;
640 ctx->lvds_dual_link_even_odd_swap = false;
642 port2 = of_graph_get_port_by_id(dev->of_node, 2);
643 port3 = of_graph_get_port_by_id(dev->of_node, 3);
649 ctx->lvds_dual_link = true;
650 /* Odd pixels to LVDS Channel A, even pixels to B */
651 ctx->lvds_dual_link_even_odd_swap = false;
653 ctx->lvds_dual_link = true;
654 /* Even pixels to LVDS Channel A, odd pixels to B */
655 ctx->lvds_dual_link_even_odd_swap = true;
658 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge);
667 ctx->panel_bridge = panel_bridge;
679 struct device *dev = ctx->dev;
687 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
688 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
695 return -EPROBE_DEFER;
705 ctx->dsi = dsi;
707 dsi->lanes = dsi_lanes;
708 dsi->format = MIPI_DSI_FMT_RGB888;
709 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
725 struct device *dev = &client->dev;
731 return -ENOMEM;
733 ctx->dev = dev;
739 ctx->reset_gpio = devm_gpiod_get_optional(ctx->dev, "reset",
741 if (IS_ERR(ctx->reset_gpio))
742 return PTR_ERR(ctx->reset_gpio);
750 ctx->regmap = devm_regmap_init_i2c(client, <9211_regmap_config);
751 if (IS_ERR(ctx->regmap))
752 return PTR_ERR(ctx->regmap);
757 ctx->bridge.funcs = <9211_funcs;
758 ctx->bridge.of_node = dev->of_node;
759 drm_bridge_add(&ctx->bridge);
763 drm_bridge_remove(&ctx->bridge);
772 drm_bridge_remove(&ctx->bridge);
799 MODULE_DESCRIPTION("Lontium LT9211 DSI/LVDS/DPI bridge driver");