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/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,mdp3-rsz.yaml30 mediatek,gce-client-reg:
34 - description: phandle of GCE
35 - description: GCE subsys id
38 description: The register of client driver can be configured by gce with
39 4 arguments defined in this property. Each GCE subsys id is mapping to
40 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
42 mediatek,gce-events:
45 to gce. The event id is defined in the gce header
46 include/dt-bindings/gce/<chip>-gce.h of each chips.
55 - mediatek,gce-client-reg
[all …]
H A Dmediatek,mdp3-wrot.yaml30 mediatek,gce-client-reg:
34 - description: phandle of GCE
35 - description: GCE subsys id
38 description: The register of client driver can be configured by gce with
39 4 arguments defined in this property. Each GCE subsys id is mapping to
40 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
42 mediatek,gce-events:
45 to gce. The event id is defined in the gce header
46 include/dt-bindings/gce/<chip>-gce.h of each chips.
64 - mediatek,gce-client-reg
[all …]
H A Dmediatek,mdp3-rdma.yaml36 mediatek,gce-client-reg:
40 - description: phandle of GCE
41 - description: GCE subsys id
44 description: The register of client driver can be configured by gce with
45 4 arguments defined in this property. Each GCE subsys id is mapping to
46 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
48 mediatek,gce-events:
51 to gce. The event id is defined in the gce header
52 include/dt-bindings/gce/<chip>-gce.h of each chips.
93 - mediatek,gce-client-reg
[all …]
H A Dmediatek,mdp3-tcc.yaml30 mediatek,gce-client-reg:
32 The register of display function block to be set by gce. There are 4 arguments,
33 such as gce node, subsys id, offset and register size. The subsys id that is
34 mapping to the register of display function blocks is defined in the gce header
35 include/dt-bindings/gce/<chip>-gce.h of each chips.
39 - description: phandle of GCE
40 - description: GCE subsys id
51 - mediatek,gce-client-reg
59 #include <dt-bindings/gce/mt8195-gce.h>
64 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
H A Dmediatek,mdp3-hdr.yaml29 mediatek,gce-client-reg:
31 The register of display function block to be set by gce. There are 4 arguments,
32 such as gce node, subsys id, offset and register size. The subsys id that is
33 mapping to the register of display function blocks is defined in the gce header
34 include/dt-bindings/gce/<chip>-gce.h of each chips.
38 - description: phandle of GCE
39 - description: GCE subsys id
50 - mediatek,gce-client-reg
58 #include <dt-bindings/gce/mt8195-gce.h>
63 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
H A Dmediatek,mdp3-fg.yaml29 mediatek,gce-client-reg:
31 The register of display function block to be set by gce. There are 4 arguments,
32 such as gce node, subsys id, offset and register size. The subsys id that is
33 mapping to the register of display function blocks is defined in the gce header
34 include/dt-bindings/gce/<chip>-gce.h of each chips.
38 - description: phandle of GCE
39 - description: GCE subsys id
50 - mediatek,gce-client-reg
58 #include <dt-bindings/gce/mt8195-gce.h>
63 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
H A Dmediatek,mdp3-tdshp.yaml29 mediatek,gce-client-reg:
31 The register of display function block to be set by gce. There are 4 arguments,
32 such as gce node, subsys id, offset and register size. The subsys id that is
33 mapping to the register of display function blocks is defined in the gce header
34 include/dt-bindings/gce/<chip>-gce.h of each chips.
38 - description: phandle of GCE
39 - description: GCE subsys id
50 - mediatek,gce-client-reg
58 #include <dt-bindings/gce/mt8195-gce.h>
63 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
H A Dmediatek,mdp3-stitch.yaml29 mediatek,gce-client-reg:
31 The register of display function block to be set by gce. There are 4 arguments,
32 such as gce node, subsys id, offset and register size. The subsys id that is
33 mapping to the register of display function blocks is defined in the gce header
34 include/dt-bindings/gce/<chip>-gce.h of each chips.
38 - description: phandle of GCE
39 - description: GCE subsys id
50 - mediatek,gce-client-reg
58 #include <dt-bindings/gce/mt8195-gce.h>
63 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dmediatek,ccorr.yaml25 mediatek,gce-client-reg:
29 - description: phandle of GCE
30 - description: GCE subsys id
33 description: The register of client driver can be configured by gce with
34 4 arguments defined in this property. Each GCE subsys id is mapping to
35 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
37 mediatek,gce-events:
40 to gce. The event id is defined in the gce header
41 include/dt-bindings/gce/<chip>-gce.h of each chips.
50 - mediatek,gce-client-reg
[all …]
H A Dmediatek,wdma.yaml26 mediatek,gce-client-reg:
30 - description: phandle of GCE
31 - description: GCE subsys id
34 description: The register of client driver can be configured by gce with
35 4 arguments defined in this property. Each GCE subsys id is mapping to
36 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
38 mediatek,gce-events:
41 to gce. The event id is defined in the gce header
42 include/dt-bindings/gce/<chip>-gce.h of each chips.
57 - mediatek,gce-client-reg
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dmediatek,gce-props.yaml4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
13 The Global Command Engine (GCE) is an instruction based, multi-threaded,
15 (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
17 and configure GCE to execute the specified instruction set in the message.
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
21 channel corresponding to a GCE hardware thread to send a message, specifying
22 that the GCE thread to configure its hardware. The mailbox provider can also
23 reserve a mailbox channel to configure GCE hardware register by the specific
24 GCE thread. This binding defines the common GCE properties for both mailbox
28 mediatek,gce-events:
[all …]
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,padding.yaml41 mediatek,gce-client-reg:
43 GCE (Global Command Engine) is a multi-core micro processor that helps
45 describes GCE client's information that is composed by 4 fields.
46 1. Phandle of the GCE (there may be several GCE processors)
48 (Please refer to include/dt-bindings/gce/<chip>-gce.h)
54 - description: Phandle of the GCE
65 - mediatek,gce-client-reg
74 #include <dt-bindings/gce/mt8195-gce.h>
85 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
H A Dmediatek,wdma.yaml50 mediatek,gce-client-reg:
51 description: The register of client driver can be configured by gce with
52 4 arguments defined in this property, such as phandle of gce, subsys id,
53 register offset and size. Each GCE subsys id is mapping to a client
54 defined in the header include/dt-bindings/gce/<chip>-gce.h.
73 #include <dt-bindings/gce/mt8173-gce.h>
87 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
H A Dmediatek,split.yaml43 mediatek,gce-client-reg:
45 The register of display function block to be set by gce. There are 4 arguments,
46 such as gce node, subsys id, offset and register size. The subsys id that is
47 mapping to the register of display function blocks is defined in the gce header
48 include/dt-bindings/gce/<chip>-gce.h of each chips.
52 - description: phandle of GCE
53 - description: GCE subsys id
84 - mediatek,gce-client-reg
H A Dmediatek,color.yaml64 mediatek,gce-client-reg:
65 description: The register of client driver can be configured by gce with
66 4 arguments defined in this property, such as phandle of gce, subsys id,
67 register offset and size. Each GCE subsys id is mapping to a client
68 defined in the header include/dt-bindings/gce/<chip>-gce.h.
108 #include <dt-bindings/gce/mt8173-gce.h>
120 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
H A Dmediatek,aal.yaml61 mediatek,gce-client-reg:
62 description: The register of client driver can be configured by gce with
63 4 arguments defined in this property, such as phandle of gce, subsys id,
64 register offset and size. Each GCE subsys id is mapping to a client
65 defined in the header include/dt-bindings/gce/<chip>-gce.h.
104 #include <dt-bindings/gce/mt8173-gce.h>
116 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
H A Dmediatek,merge.yaml76 mediatek,gce-client-reg:
77 description: The register of client driver can be configured by gce with
78 4 arguments defined in this property, such as phandle of gce, subsys id,
79 register offset and size. Each GCE subsys id is mapping to a client
80 defined in the header include/dt-bindings/gce/<chip>-gce.h.
/linux/drivers/mailbox/
H A Dmtk-cmdq-mailbox.c97 /* Convert DMA addr (PA or IOVA) to GCE readable addr */ in cmdq_convert_gce_addr()
103 /* Revert GCE readable addr to DMA addr (PA or IOVA) */ in cmdq_revert_gce_addr()
140 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n", in cmdq_thread_suspend()
175 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n", in cmdq_thread_reset()
189 /* notify GCE to re-fetch commands by setting GCE thread PC */
261 * reset / disable this GCE thread, so we need to check the enable in cmdq_thread_irq_handler()
262 * bit of this GCE thread. in cmdq_thread_irq_handler()
544 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n", in cmdq_mbox_flush()
579 static const char * const gce_name = "gce"; in cmdq_get_clocks()
595 "failed to get gce clock\n"); in cmdq_get_clocks()
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi14 #include <dt-bindings/gce/mt8173-gce.h>
634 gce: mailbox@10212000 { label
635 compatible = "mediatek,mt8173-gce";
639 clock-names = "gce";
1013 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1014 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1015 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1090 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1100 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1110 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
[all …]
H A Dmt8195.dtsi9 #include <dt-bindings/gce/mt8195-gce.h>
917 compatible = "mediatek,mt8195-gce";
925 compatible = "mediatek,mt8195-gce";
2054 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2060 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2061 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2078 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2085 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2092 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2100 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
H A Dmt8183.dtsi9 #include <dt-bindings/gce/mt8183-gce.h>
1065 gce: mailbox@10238000 { label
1066 compatible = "mediatek,mt8183-gce";
1071 clock-names = "gce";
1667 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1668 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1669 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1690 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1691 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1697 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
[all …]
H A Dmt8196-gce.h10 /* GCE Thread Priority
11 * The GCE core has multiple GCE threads, each of which can independently
13 * However, the GCE threads on the same core cannot run in parallel.
14 * Different GCE threads can determine thread priority based on the scenario,
32 * which are sent from the corresponding hardware to the GCE.
33 * Each hardware event signal corresponds to an event ID in the GCE.
36 * the GCE to execute operations in the instructions for that event ID.
244 * which are sent from the corresponding hardware to the GCE.
245 * Each hardware event signal corresponds to an event ID in the GCE.
248 * the GCE to execute operations in the instructions for that event ID.
[all …]
H A Dmt8192.dtsi9 #include <dt-bindings/gce/mt8192-gce.h>
744 gce: mailbox@10228000 { label
745 compatible = "mediatek,mt8192-gce";
750 clock-names = "gce";
1457 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1458 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1459 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1467 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1468 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1512 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
/linux/include/dt-bindings/gce/
H A Dmt8186-gce.h14 /* GCE thread priority */
27 /* GCE subsys table */
60 /* GCE General Purpose Register (GPR) support
63 /* GCE: write mask */
89 /* GCE hardware events */
349 * Following definitions are gce sw token which may use by clients
396 /* Resource lock event to control resource in GCE thread */
H A Dmt8173-gce.h11 /* GCE HW thread priority */
15 /* GCE SUBSYS */
20 /* GCE HW EVENT */

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