14ed545e7Sjason-jh.lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24ed545e7Sjason-jh.lin%YAML 1.2 34ed545e7Sjason-jh.lin--- 44ed545e7Sjason-jh.lin$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml# 54ed545e7Sjason-jh.lin$schema: http://devicetree.org/meta-schemas/core.yaml# 64ed545e7Sjason-jh.lin 74ed545e7Sjason-jh.lintitle: Mediatek display merge 84ed545e7Sjason-jh.lin 94ed545e7Sjason-jh.linmaintainers: 104ed545e7Sjason-jh.lin - Chun-Kuang Hu <chunkuang.hu@kernel.org> 114ed545e7Sjason-jh.lin - Philipp Zabel <p.zabel@pengutronix.de> 124ed545e7Sjason-jh.lin 134ed545e7Sjason-jh.lindescription: | 144ed545e7Sjason-jh.lin Mediatek display merge, namely MERGE, is used to merge two slice-per-line 154ed545e7Sjason-jh.lin inputs into one side-by-side output. 164ed545e7Sjason-jh.lin MERGE device node must be siblings to the central MMSYS_CONFIG node. 174ed545e7Sjason-jh.lin For a description of the MMSYS_CONFIG binding, see 184ed545e7Sjason-jh.lin Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 194ed545e7Sjason-jh.lin for details. 204ed545e7Sjason-jh.lin 214ed545e7Sjason-jh.linproperties: 224ed545e7Sjason-jh.lin compatible: 234ed545e7Sjason-jh.lin oneOf: 24112d5560SKrzysztof Kozlowski - enum: 25112d5560SKrzysztof Kozlowski - mediatek,mt8173-disp-merge 26112d5560SKrzysztof Kozlowski - mediatek,mt8195-disp-merge 27*4ae88e9cSMoudy Ho - mediatek,mt8195-mdp3-merge 28400ab909SAngeloGioacchino Del Regno - items: 29400ab909SAngeloGioacchino Del Regno - const: mediatek,mt6795-disp-merge 30400ab909SAngeloGioacchino Del Regno - const: mediatek,mt8173-disp-merge 31c2501ad2SHsiao Chien Sung - items: 32c2501ad2SHsiao Chien Sung - const: mediatek,mt8188-disp-merge 33c2501ad2SHsiao Chien Sung - const: mediatek,mt8195-disp-merge 344ed545e7Sjason-jh.lin 354ed545e7Sjason-jh.lin reg: 364ed545e7Sjason-jh.lin maxItems: 1 374ed545e7Sjason-jh.lin 384ed545e7Sjason-jh.lin interrupts: 394ed545e7Sjason-jh.lin maxItems: 1 404ed545e7Sjason-jh.lin 414ed545e7Sjason-jh.lin power-domains: 424ed545e7Sjason-jh.lin description: A phandle and PM domain specifier as defined by bindings of 434ed545e7Sjason-jh.lin the power controller specified by phandle. See 444ed545e7Sjason-jh.lin Documentation/devicetree/bindings/power/power-domain.yaml for details. 454ed545e7Sjason-jh.lin 464ed545e7Sjason-jh.lin clocks: 47bff4e302SAngeloGioacchino Del Regno minItems: 1 481cffdf60Sjason-jh.lin maxItems: 2 491cffdf60Sjason-jh.lin 501cffdf60Sjason-jh.lin clock-names: 51bff4e302SAngeloGioacchino Del Regno oneOf: 52bff4e302SAngeloGioacchino Del Regno - items: 53bff4e302SAngeloGioacchino Del Regno - const: merge 54bff4e302SAngeloGioacchino Del Regno - items: 551cffdf60Sjason-jh.lin - const: merge 561cffdf60Sjason-jh.lin - const: merge_async 571cffdf60Sjason-jh.lin 581cffdf60Sjason-jh.lin mediatek,merge-fifo-en: 591cffdf60Sjason-jh.lin description: 601cffdf60Sjason-jh.lin The setting of merge fifo is mainly provided for the display latency 611cffdf60Sjason-jh.lin buffer to ensure that the back-end panel display data will not be 621cffdf60Sjason-jh.lin underrun, a little more data is needed in the fifo. 631cffdf60Sjason-jh.lin According to the merge fifo settings, when the water level is detected 641cffdf60Sjason-jh.lin to be insufficient, it will trigger RDMA sending ultra and preulra 651cffdf60Sjason-jh.lin command to SMI to speed up the data rate. 661cffdf60Sjason-jh.lin type: boolean 674ed545e7Sjason-jh.lin 6887e70353SNancy.Lin mediatek,merge-mute: 6987e70353SNancy.Lin description: Support mute function. Mute the content of merge output. 7087e70353SNancy.Lin type: boolean 7187e70353SNancy.Lin 724ed545e7Sjason-jh.lin mediatek,gce-client-reg: 734ed545e7Sjason-jh.lin description: The register of client driver can be configured by gce with 744ed545e7Sjason-jh.lin 4 arguments defined in this property, such as phandle of gce, subsys id, 754ed545e7Sjason-jh.lin register offset and size. Each GCE subsys id is mapping to a client 764ed545e7Sjason-jh.lin defined in the header include/dt-bindings/gce/<chip>-gce.h. 774ed545e7Sjason-jh.lin $ref: /schemas/types.yaml#/definitions/phandle-array 784ed545e7Sjason-jh.lin maxItems: 1 794ed545e7Sjason-jh.lin 801cffdf60Sjason-jh.lin resets: 811cffdf60Sjason-jh.lin description: reset controller 821cffdf60Sjason-jh.lin See Documentation/devicetree/bindings/reset/reset.txt for details. 831cffdf60Sjason-jh.lin maxItems: 1 841cffdf60Sjason-jh.lin 854ed545e7Sjason-jh.linrequired: 864ed545e7Sjason-jh.lin - compatible 874ed545e7Sjason-jh.lin - reg 884ed545e7Sjason-jh.lin - power-domains 894ed545e7Sjason-jh.lin - clocks 904ed545e7Sjason-jh.lin 914ed545e7Sjason-jh.linadditionalProperties: false 924ed545e7Sjason-jh.lin 934ed545e7Sjason-jh.linexamples: 944ed545e7Sjason-jh.lin - | 95bff4e302SAngeloGioacchino Del Regno #include <dt-bindings/interrupt-controller/arm-gic.h> 96bff4e302SAngeloGioacchino Del Regno #include <dt-bindings/clock/mt8173-clk.h> 97bff4e302SAngeloGioacchino Del Regno #include <dt-bindings/power/mt8173-power.h> 98bff4e302SAngeloGioacchino Del Regno 99bff4e302SAngeloGioacchino Del Regno soc { 100bff4e302SAngeloGioacchino Del Regno #address-cells = <2>; 101bff4e302SAngeloGioacchino Del Regno #size-cells = <2>; 1024ed545e7Sjason-jh.lin 1034ed545e7Sjason-jh.lin merge@14017000 { 1044ed545e7Sjason-jh.lin compatible = "mediatek,mt8173-disp-merge"; 1054ed545e7Sjason-jh.lin reg = <0 0x14017000 0 0x1000>; 1064ed545e7Sjason-jh.lin power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1074ed545e7Sjason-jh.lin clocks = <&mmsys CLK_MM_DISP_MERGE>; 108bff4e302SAngeloGioacchino Del Regno clock-names = "merge"; 109bff4e302SAngeloGioacchino Del Regno }; 1104ed545e7Sjason-jh.lin }; 111