14ad7b396SMoudy Ho# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24ad7b396SMoudy Ho%YAML 1.2 34ad7b396SMoudy Ho--- 44ad7b396SMoudy Ho$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml# 54ad7b396SMoudy Ho$schema: http://devicetree.org/meta-schemas/core.yaml# 64ad7b396SMoudy Ho 74ad7b396SMoudy Hotitle: MediaTek Resizer 84ad7b396SMoudy Ho 94ad7b396SMoudy Homaintainers: 104ad7b396SMoudy Ho - Matthias Brugger <matthias.bgg@gmail.com> 114ad7b396SMoudy Ho - Moudy Ho <moudy.ho@mediatek.com> 124ad7b396SMoudy Ho 134ad7b396SMoudy Hodescription: | 144ad7b396SMoudy Ho One of Media Data Path 3 (MDP3) components used to do frame resizing. 154ad7b396SMoudy Ho 164ad7b396SMoudy Hoproperties: 174ad7b396SMoudy Ho compatible: 18*ba61ee5bSMoudy Ho oneOf: 194ad7b396SMoudy Ho - enum: 204ad7b396SMoudy Ho - mediatek,mt8183-mdp3-rsz 21*ba61ee5bSMoudy Ho - items: 22*ba61ee5bSMoudy Ho - enum: 23*ba61ee5bSMoudy Ho - mediatek,mt8195-mdp3-rsz 24*ba61ee5bSMoudy Ho - const: mediatek,mt8183-mdp3-rsz 254ad7b396SMoudy Ho 264ad7b396SMoudy Ho reg: 274ad7b396SMoudy Ho maxItems: 1 284ad7b396SMoudy Ho 294ad7b396SMoudy Ho mediatek,gce-client-reg: 304ad7b396SMoudy Ho $ref: /schemas/types.yaml#/definitions/phandle-array 314ad7b396SMoudy Ho items: 324ad7b396SMoudy Ho items: 334ad7b396SMoudy Ho - description: phandle of GCE 344ad7b396SMoudy Ho - description: GCE subsys id 354ad7b396SMoudy Ho - description: register offset 364ad7b396SMoudy Ho - description: register size 374ad7b396SMoudy Ho description: The register of client driver can be configured by gce with 384ad7b396SMoudy Ho 4 arguments defined in this property. Each GCE subsys id is mapping to 394ad7b396SMoudy Ho a client defined in the header include/dt-bindings/gce/<chip>-gce.h. 404ad7b396SMoudy Ho 414ad7b396SMoudy Ho mediatek,gce-events: 424ad7b396SMoudy Ho description: 434ad7b396SMoudy Ho The event id which is mapping to the specific hardware event signal 444ad7b396SMoudy Ho to gce. The event id is defined in the gce header 454ad7b396SMoudy Ho include/dt-bindings/gce/<chip>-gce.h of each chips. 464ad7b396SMoudy Ho $ref: /schemas/types.yaml#/definitions/uint32-array 474ad7b396SMoudy Ho 484ad7b396SMoudy Ho clocks: 494ad7b396SMoudy Ho minItems: 1 504ad7b396SMoudy Ho 514ad7b396SMoudy Horequired: 524ad7b396SMoudy Ho - compatible 534ad7b396SMoudy Ho - reg 544ad7b396SMoudy Ho - mediatek,gce-client-reg 554ad7b396SMoudy Ho - mediatek,gce-events 564ad7b396SMoudy Ho - clocks 574ad7b396SMoudy Ho 584ad7b396SMoudy HoadditionalProperties: false 594ad7b396SMoudy Ho 604ad7b396SMoudy Hoexamples: 614ad7b396SMoudy Ho - | 624ad7b396SMoudy Ho #include <dt-bindings/clock/mt8183-clk.h> 634ad7b396SMoudy Ho #include <dt-bindings/gce/mt8183-gce.h> 644ad7b396SMoudy Ho 654ad7b396SMoudy Ho mdp3_rsz0: mdp3-rsz0@14003000 { 664ad7b396SMoudy Ho compatible = "mediatek,mt8183-mdp3-rsz"; 674ad7b396SMoudy Ho reg = <0x14003000 0x1000>; 684ad7b396SMoudy Ho mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; 694ad7b396SMoudy Ho mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, 704ad7b396SMoudy Ho <CMDQ_EVENT_MDP_RSZ0_EOF>; 714ad7b396SMoudy Ho clocks = <&mmsys CLK_MM_MDP_RSZ0>; 724ad7b396SMoudy Ho }; 734ad7b396SMoudy Ho 744ad7b396SMoudy Ho mdp3_rsz1: mdp3-rsz1@14004000 { 754ad7b396SMoudy Ho compatible = "mediatek,mt8183-mdp3-rsz"; 764ad7b396SMoudy Ho reg = <0x14004000 0x1000>; 774ad7b396SMoudy Ho mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; 784ad7b396SMoudy Ho mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, 794ad7b396SMoudy Ho <CMDQ_EVENT_MDP_RSZ1_EOF>; 804ad7b396SMoudy Ho clocks = <&mmsys CLK_MM_MDP_RSZ1>; 814ad7b396SMoudy Ho }; 82