14ed545e7Sjason-jh.lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24ed545e7Sjason-jh.lin%YAML 1.2 34ed545e7Sjason-jh.lin--- 44ed545e7Sjason-jh.lin$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml# 54ed545e7Sjason-jh.lin$schema: http://devicetree.org/meta-schemas/core.yaml# 64ed545e7Sjason-jh.lin 74ed545e7Sjason-jh.lintitle: Mediatek display split 84ed545e7Sjason-jh.lin 94ed545e7Sjason-jh.linmaintainers: 104ed545e7Sjason-jh.lin - Chun-Kuang Hu <chunkuang.hu@kernel.org> 114ed545e7Sjason-jh.lin - Philipp Zabel <p.zabel@pengutronix.de> 124ed545e7Sjason-jh.lin 134ed545e7Sjason-jh.lindescription: | 144ed545e7Sjason-jh.lin Mediatek display split, namely SPLIT, is used to split stream to two 154ed545e7Sjason-jh.lin encoders. 164ed545e7Sjason-jh.lin SPLIT device node must be siblings to the central MMSYS_CONFIG node. 174ed545e7Sjason-jh.lin For a description of the MMSYS_CONFIG binding, see 184ed545e7Sjason-jh.lin Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 194ed545e7Sjason-jh.lin for details. 204ed545e7Sjason-jh.lin 214ed545e7Sjason-jh.linproperties: 224ed545e7Sjason-jh.lin compatible: 234ed545e7Sjason-jh.lin oneOf: 24112d5560SKrzysztof Kozlowski - enum: 25112d5560SKrzysztof Kozlowski - mediatek,mt8173-disp-split 26739058a9SMoudy Ho - mediatek,mt8195-mdp3-split 275dfd9bb3SAngeloGioacchino Del Regno - items: 285dfd9bb3SAngeloGioacchino Del Regno - const: mediatek,mt6795-disp-split 295dfd9bb3SAngeloGioacchino Del Regno - const: mediatek,mt8173-disp-split 304ed545e7Sjason-jh.lin 314ed545e7Sjason-jh.lin reg: 324ed545e7Sjason-jh.lin maxItems: 1 334ed545e7Sjason-jh.lin 344ed545e7Sjason-jh.lin interrupts: 354ed545e7Sjason-jh.lin maxItems: 1 364ed545e7Sjason-jh.lin 374ed545e7Sjason-jh.lin power-domains: 384ed545e7Sjason-jh.lin description: A phandle and PM domain specifier as defined by bindings of 394ed545e7Sjason-jh.lin the power controller specified by phandle. See 404ed545e7Sjason-jh.lin Documentation/devicetree/bindings/power/power-domain.yaml for details. 41*3ad0edc4SMoudy Ho maxItems: 1 424ed545e7Sjason-jh.lin 43739058a9SMoudy Ho mediatek,gce-client-reg: 44739058a9SMoudy Ho description: 45739058a9SMoudy Ho The register of display function block to be set by gce. There are 4 arguments, 46739058a9SMoudy Ho such as gce node, subsys id, offset and register size. The subsys id that is 47739058a9SMoudy Ho mapping to the register of display function blocks is defined in the gce header 48739058a9SMoudy Ho include/dt-bindings/gce/<chip>-gce.h of each chips. 49739058a9SMoudy Ho $ref: /schemas/types.yaml#/definitions/phandle-array 50739058a9SMoudy Ho items: 51739058a9SMoudy Ho items: 52739058a9SMoudy Ho - description: phandle of GCE 53739058a9SMoudy Ho - description: GCE subsys id 54739058a9SMoudy Ho - description: register offset 55739058a9SMoudy Ho - description: register size 56739058a9SMoudy Ho maxItems: 1 57739058a9SMoudy Ho 584ed545e7Sjason-jh.lin clocks: 594ed545e7Sjason-jh.lin items: 604ed545e7Sjason-jh.lin - description: SPLIT Clock 61*3ad0edc4SMoudy Ho - description: Used for interfacing with the HDMI RX signal source. 62*3ad0edc4SMoudy Ho - description: Paired with receiving HDMI RX metadata. 63*3ad0edc4SMoudy Ho minItems: 1 644ed545e7Sjason-jh.lin 654ed545e7Sjason-jh.linrequired: 664ed545e7Sjason-jh.lin - compatible 674ed545e7Sjason-jh.lin - reg 684ed545e7Sjason-jh.lin - power-domains 694ed545e7Sjason-jh.lin - clocks 704ed545e7Sjason-jh.lin 71739058a9SMoudy HoallOf: 72739058a9SMoudy Ho - if: 73739058a9SMoudy Ho properties: 74739058a9SMoudy Ho compatible: 75739058a9SMoudy Ho contains: 76739058a9SMoudy Ho const: mediatek,mt8195-mdp3-split 77739058a9SMoudy Ho 78739058a9SMoudy Ho then: 79*3ad0edc4SMoudy Ho properties: 80*3ad0edc4SMoudy Ho clocks: 81*3ad0edc4SMoudy Ho minItems: 3 82*3ad0edc4SMoudy Ho 83739058a9SMoudy Ho required: 84739058a9SMoudy Ho - mediatek,gce-client-reg 85739058a9SMoudy Ho 86*3ad0edc4SMoudy Ho - if: 87*3ad0edc4SMoudy Ho properties: 88*3ad0edc4SMoudy Ho compatible: 89*3ad0edc4SMoudy Ho contains: 90*3ad0edc4SMoudy Ho const: mediatek,mt8173-disp-split 91*3ad0edc4SMoudy Ho 92*3ad0edc4SMoudy Ho then: 93*3ad0edc4SMoudy Ho properties: 94*3ad0edc4SMoudy Ho clocks: 95*3ad0edc4SMoudy Ho maxItems: 1 96*3ad0edc4SMoudy Ho 974ed545e7Sjason-jh.linadditionalProperties: false 984ed545e7Sjason-jh.lin 994ed545e7Sjason-jh.linexamples: 1004ed545e7Sjason-jh.lin - | 101bff4e302SAngeloGioacchino Del Regno #include <dt-bindings/clock/mt8173-clk.h> 102bff4e302SAngeloGioacchino Del Regno #include <dt-bindings/power/mt8173-power.h> 103bff4e302SAngeloGioacchino Del Regno 104bff4e302SAngeloGioacchino Del Regno soc { 105bff4e302SAngeloGioacchino Del Regno #address-cells = <2>; 106bff4e302SAngeloGioacchino Del Regno #size-cells = <2>; 1074ed545e7Sjason-jh.lin 1084ed545e7Sjason-jh.lin split0: split@14018000 { 1094ed545e7Sjason-jh.lin compatible = "mediatek,mt8173-disp-split"; 1104ed545e7Sjason-jh.lin reg = <0 0x14018000 0 0x1000>; 1114ed545e7Sjason-jh.lin power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1124ed545e7Sjason-jh.lin clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1134ed545e7Sjason-jh.lin }; 114bff4e302SAngeloGioacchino Del Regno }; 115