1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * 5 */ 6 7 #ifndef __DTS_GCE_MT8196_H 8 #define __DTS_GCE_MT8196_H 9 10 /* GCE Thread Priority 11 * The GCE core has multiple GCE threads, each of which can independently 12 * execute its own sequence of instructions. 13 * However, the GCE threads on the same core cannot run in parallel. 14 * Different GCE threads can determine thread priority based on the scenario, 15 * thereby serving different user needs. 16 * 17 * Low priority thread is executed when no high priority thread is active. 18 * Same priority thread is scheduled by round robin. 19 */ 20 #define CMDQ_THR_PRIO_LOWEST 0 21 #define CMDQ_THR_PRIO_1 1 22 #define CMDQ_THR_PRIO_2 2 23 #define CMDQ_THR_PRIO_3 3 24 #define CMDQ_THR_PRIO_4 4 25 #define CMDQ_THR_PRIO_5 5 26 #define CMDQ_THR_PRIO_6 6 27 #define CMDQ_THR_PRIO_HIGHEST 7 28 29 /* 30 * GCE0 Hardware Event IDs 31 * Different SoCs will have varying numbers of hardware event signals, 32 * which are sent from the corresponding hardware to the GCE. 33 * Each hardware event signal corresponds to an event ID in the GCE. 34 * The CMDQ driver can use the following event ID definitions to allow 35 * the client driver to use wait and clear APIs provided by CMDQ, enabling 36 * the GCE to execute operations in the instructions for that event ID. 37 * 38 * The event IDs of GCE0 are mainly used by display hardware. 39 */ 40 /* CMDQ_EVENT_DISP0_STREAM_SOF0 ~ 15: 0 ~ 15 */ 41 #define CMDQ_EVENT_DISP0_STREAM_SOF(n) (0 + (n)) 42 /* CMDQ_EVENT_DISP0_FRAME_DONE_SEL0 ~ 15: 16 ~ 31 */ 43 #define CMDQ_EVENT_DISP0_FRAME_DONE_SEL(n) (16 + (n)) 44 #define CMDQ_EVENT_DISP0_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 32 45 #define CMDQ_EVENT_DISP0_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 33 46 #define CMDQ_EVENT_DISP0_DISP_POSTMASK1_RST_DONE_ENG_EVENT 34 47 #define CMDQ_EVENT_DISP0_DISP_POSTMASK0_RST_DONE_ENG_EVENT 35 48 #define CMDQ_EVENT_DISP0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 36 49 /* CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT0 ~ 15: 37 ~ 52 */ 50 #define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT(n) (37 + (n)) 51 #define CMDQ_EVENT_DISP0_DISP_MUTEX0_GET_RELEASE_ENG_EVENT 53 52 #define CMDQ_EVENT_DISP0_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 54 53 /* CMDQ_EVENT_DISP1_STREAM_SOF0 ~ 15: 55 ~ 70 */ 54 #define CMDQ_EVENT_DISP1_STREAM_SOF(n) (55 + (n)) 55 /* CMDQ_EVENT_DISP1_FRAME_DONE_SEL0 ~ 15: 71 ~ 86 */ 56 #define CMDQ_EVENT_DISP1_FRAME_DONE_SEL(n) (71 + (n)) 57 /* CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT0 ~ 15: 87 ~ 102 */ 58 #define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT(n) (87 + (n)) 59 /* CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 103 ~ 118 */ 60 #define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT(n) (103 + (n)) 61 #define CMDQ_EVENT_DISP1_OCIP_SUBSYS_SRAM_ISOINT_ENG_EVENT 119 62 #define CMDQ_EVENT_DISP1_DISP_WDMA4_TARGET_LINE_END_ENG_EVENT 120 63 #define CMDQ_EVENT_DISP1_DISP_WDMA4_SW_RST_DONE_ENG_EVENT 121 64 #define CMDQ_EVENT_DISP1_DISP_WDMA3_TARGET_LINE_END_ENG_EVENT 122 65 #define CMDQ_EVENT_DISP1_DISP_WDMA3_SW_RST_DONE_ENG_EVENT 123 66 #define CMDQ_EVENT_DISP1_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT 124 67 #define CMDQ_EVENT_DISP1_DISP_WDMA2_SW_RST_DONE_ENG_EVENT 125 68 #define CMDQ_EVENT_DISP1_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 126 69 #define CMDQ_EVENT_DISP1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 127 70 #define CMDQ_EVENT_DISP1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 128 71 #define CMDQ_EVENT_DISP1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 129 72 #define CMDQ_EVENT_DISP1_DISP_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 130 73 #define CMDQ_EVENT_DISP1_DISP_GDMA0_SW_RST_DONE_ENG_EVENT 131 74 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_START_ENG_EVENT 132 75 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_END_ENG_EVENT 133 76 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VRR_VFP_LAST_SAFE_BLANK_ENG_EVENT 134 77 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_START_ENG_EVENT 135 78 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_LAST_LINE_ENG_EVENT 136 79 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VDE_END_ENG_EVENT 137 80 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TRIGGER_LOOP_CLR_ENG_EVENT 138 81 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE1_ENG_EVENT 139 82 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE0_ENG_EVENT 140 83 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_START_ENG_EVENT 141 84 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_END_ENG_EVENT 142 85 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_START_ENG_EVENT 143 86 #define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_END_ENG_EVENT 144 87 /* CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT0 ~ 10: 145 ~ 155 */ 88 #define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT(n) (145 + (n)) 89 /* CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT0 ~ 21: 156 ~ 177 */ 90 #define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT(n) (156 + (n)) 91 /* CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT0 ~ 10: 178 ~ 188 */ 92 #define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT(n) (178 + (n)) 93 #define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_START_ENG_EVENT 189 94 #define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_END_ENG_EVENT 190 95 #define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_START_ENG_EVENT 191 96 #define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_END_ENG_EVENT 192 97 #define CMDQ_EVENT_DISP1_DISP_DP_INTF1_TARGET_LINE_ENG_EVENT 193 98 #define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_START_ENG_EVENT 194 99 #define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_END_ENG_EVENT 195 100 #define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_START_ENG_EVENT 196 101 #define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_END_ENG_EVENT 197 102 #define CMDQ_EVENT_DISP1_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT 198 103 /* CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT0 ~ 10: 199 ~ 209 */ 104 #define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT(n) (199 + (n)) 105 /* CMDQ_EVENT_MML0_STREAM_SOF0 ~ 15: 210 ~ 225 */ 106 #define CMDQ_EVENT_MML0_STREAM_SOF(n) (210 + (n)) 107 /* CMDQ_EVENT_MML0_FRAME_DONE_SEL0 ~ 15: 226 ~ 241 */ 108 #define CMDQ_EVENT_MML0_FRAME_DONE_SEL(n) (226 + (n)) 109 /* CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 242 ~ 257 */ 110 #define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT(n) (242 + (n)) 111 #define CMDQ_EVENT_MML0_MDP_WROT2_SW_RST_DONE_ENG_EVENT 258 112 #define CMDQ_EVENT_MML0_MDP_WROT1_SW_RST_DONE_ENG_EVENT 259 113 #define CMDQ_EVENT_MML0_MDP_WROT0_SW_RST_DONE_ENG_EVENT 260 114 #define CMDQ_EVENT_MML0_MDP_RROT0_SW_RST_DONE_ENG_EVENT 261 115 #define CMDQ_EVENT_MML0_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 262 116 #define CMDQ_EVENT_MML0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 263 117 #define CMDQ_EVENT_MML0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 264 118 #define CMDQ_EVENT_MML0_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 265 119 #define CMDQ_EVENT_MML0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 266 120 #define CMDQ_EVENT_MML0_DISP_MUTEX0_GET_RLZ_ENG_EVENT 267 121 /* CMDQ_EVENT_MML1_STREAM_SOF0 ~ 15: 268 ~ 283 */ 122 #define CMDQ_EVENT_MML1_STREAM_SOF(n) (268 + (n)) 123 /* CMDQ_EVENT_MML1_FRAME_DONE_SEL0 ~ 15: 284 ~ 299 */ 124 #define CMDQ_EVENT_MML1_FRAME_DONE_SEL(n) (284 + (n)) 125 /* CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 300 ~ 315 */ 126 #define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT(n) (300 + (n)) 127 #define CMDQ_EVENT_MML1_MDP_WROT2_SW_RST_DONE_ENG_EVENT 316 128 #define CMDQ_EVENT_MML1_MDP_WROT1_SW_RST_DONE_ENG_EVENT 317 129 #define CMDQ_EVENT_MML1_MDP_WROT0_SW_RST_DONE_ENG_EVENT 318 130 #define CMDQ_EVENT_MML1_MDP_RROT0_SW_RST_DONE_ENG_EVENT 319 131 #define CMDQ_EVENT_MML1_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 320 132 #define CMDQ_EVENT_MML1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 321 133 #define CMDQ_EVENT_MML1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 322 134 #define CMDQ_EVENT_MML1_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 323 135 #define CMDQ_EVENT_MML1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 324 136 #define CMDQ_EVENT_MML1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 325 137 /* CMDQ_EVENT_OVL0_STREAM_SOF0 ~ 15: 326 ~ 341 */ 138 #define CMDQ_EVENT_OVL0_STREAM_SOF(n) (326 + (n)) 139 /* CMDQ_EVENT_OVL0_FRAME_DONE_SEL0 ~ 15: 342 ~ 357 */ 140 #define CMDQ_EVENT_OVL0_FRAME_DONE_SEL(n) (342 + (n)) 141 #define CMDQ_EVENT_OVL0_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 358 142 #define CMDQ_EVENT_OVL0_OVL_MUTEX0_TIMEOUT_ENG_EVENT 359 143 /* CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 360 ~ 375 */ 144 #define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n) (360 + (n)) 145 #define CMDQ_EVENT_OVL0_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 376 146 #define CMDQ_EVENT_OVL0_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 377 147 #define CMDQ_EVENT_OVL0_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 378 148 #define CMDQ_EVENT_OVL0_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 379 149 #define CMDQ_EVENT_OVL0_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 380 150 #define CMDQ_EVENT_OVL0_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 381 151 #define CMDQ_EVENT_OVL0_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 382 152 #define CMDQ_EVENT_OVL0_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 383 153 #define CMDQ_EVENT_OVL0_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 384 154 #define CMDQ_EVENT_OVL0_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 385 155 #define CMDQ_EVENT_OVL0_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 386 156 #define CMDQ_EVENT_OVL0_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 387 157 #define CMDQ_EVENT_OVL0_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 388 158 #define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 389 159 #define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 390 160 #define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 391 161 #define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 392 162 #define CMDQ_EVENT_OVL0_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 393 163 /* CMDQ_EVENT_OVL1_STREAM_SOF0 ~ 15: 394 ~ 409 */ 164 #define CMDQ_EVENT_OVL1_STREAM_SOF(n) (394 + (n)) 165 /* CMDQ_EVENT_OVL1_FRAME_DONE_SEL0 ~ 15: 410 ~ 425 */ 166 #define CMDQ_EVENT_OVL1_FRAME_DONE_SEL(n) (410 + (n)) 167 #define CMDQ_EVENT_OVL1_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 426 168 #define CMDQ_EVENT_OVL1_OVL_MUTEX0_TIMEOUT_ENG_EVENT 427 169 /* CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 428 ~ 443 */ 170 #define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n) (428 + (n)) 171 #define CMDQ_EVENT_OVL1_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 444 172 #define CMDQ_EVENT_OVL1_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 445 173 #define CMDQ_EVENT_OVL1_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 446 174 #define CMDQ_EVENT_OVL1_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 447 175 #define CMDQ_EVENT_OVL1_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 448 176 #define CMDQ_EVENT_OVL1_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 449 177 #define CMDQ_EVENT_OVL1_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 450 178 #define CMDQ_EVENT_OVL1_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 451 179 #define CMDQ_EVENT_OVL1_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 452 180 #define CMDQ_EVENT_OVL1_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 453 181 #define CMDQ_EVENT_OVL1_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 454 182 #define CMDQ_EVENT_OVL1_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 455 183 #define CMDQ_EVENT_OVL1_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 456 184 #define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 457 185 #define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 458 186 #define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 459 187 #define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 460 188 #define CMDQ_EVENT_OVL1_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 461 189 #define CMDQ_EVENT_DPC_DT_DONE0 462 190 #define CMDQ_EVENT_DPC_DT_DONE1 463 191 #define CMDQ_EVENT_DPC_DT_DONE2_0_MERGE 464 192 #define CMDQ_EVENT_DPC_DT_DONE2_1_MERGE 465 193 #define CMDQ_EVENT_DPC_DT_DONE2_2_MERGE 466 194 #define CMDQ_EVENT_DPC_DT_DONE2_3_MERGE 467 195 #define CMDQ_EVENT_DPC_DT_DONE3 468 196 #define CMDQ_EVENT_DPC_DT_DONE4_MERGE 469 197 #define CMDQ_EVENT_DPC_DT_DONE5 470 198 #define CMDQ_EVENT_DPC_DT_DONE6_0_MERGE 471 199 #define CMDQ_EVENT_DPC_DT_DONE6_1_MERGE 472 200 #define CMDQ_EVENT_DPC_DT_DONE6_2_MERGE 473 201 #define CMDQ_EVENT_DPC_DT_DONE6_3_MERGE 474 202 #define CMDQ_EVENT_DPC_DT_DONE7 475 203 #define CMDQ_EVENT_DPC_DT_DONE32_MERGE 476 204 #define CMDQ_EVENT_DPC_DT_DONE33 477 205 #define CMDQ_EVENT_DPC_DT_DONE34_0 478 206 #define CMDQ_EVENT_DPC_DT_DONE35 479 207 #define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_ON_BEFORE_OFF 480 208 #define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_PRETE_BEFORE_ON 481 209 #define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_ON_BEFORE_OFF 482 210 #define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_PRETE_BEFORE_ON 483 211 #define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_ON_BEFORE_OFF 484 212 #define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_PRETE_BEFORE_ON 485 213 #define CMDQ_EVENT_DPC_DISP_SW_CONFIG_WHEN_MTCMOS_OFF 486 214 #define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_ON_BEFORE_OFF 487 215 #define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_PRETE_BEFORE_ON 488 216 #define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_ON_BEFORE_OFF 489 217 #define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_PRETE_BEFORE_ON 490 218 #define CMDQ_EVENT_DPC_MML_SB_DT_ERR_ON_BEFORE_OFF 491 219 #define CMDQ_EVENT_DPC_MML_SB_DT_ERR_PRETE_BEFORE_ON 492 220 #define CMDQ_EVENT_DPC_MML_SW_CONFIG_WHEN_MTCMOS_OFF 493 221 /* CMDQ_EVENT_DPTX_DPTX_EVENT0 ~ 3: 494 ~ 497 */ 222 #define CMDQ_EVENT_DPTX_DPTX_EVENT(n) (494 + (n)) 223 /* CMDQ_EVENT_EDPTX_EDPTX_EVENT0 ~ 1: 498 ~ 499 */ 224 #define CMDQ_EVENT_EDPTX_EDPTX_EVENT(n) (498 + (n)) 225 226 #define CMDQ_EVENT_DSI0_TE_I_DSI0_TE_I 898 227 #define CMDQ_EVENT_DSI1_TE_I_DSI1_TE_I 899 228 #define CMDQ_EVENT_DSI2_TE_I_DSI2_TE_I 900 229 /* CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK0 ~ 23: 901 ~ 924 */ 230 #define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK(n) (901 + (n)) 231 /* CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX0 ~ 1: 925 ~ 926 */ 232 #define CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX(n) (925 + (n)) 233 /* CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P10 ~ 1: 927 ~ 928 */ 234 #define CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P1(n) (927 + (n)) 235 /* CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX0 ~ 1: 929 ~ 930 */ 236 #define CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX(n) (929 + (n)) 237 #define CMDQ_EVENT_DSI3_TE_I_DSI3_TE_I 931 238 #define CMDQ_EVENT_SPI0_FINISH_EVENT_DSI4_TE_I 932 239 #define CMDQ_EVENT_SPI0_EVENT_EVENT_DSI5_TE_I 933 240 241 /* 242 * GCE1 Hardware Event IDs 243 * Different SoCs will have varying numbers of hardware event signals, 244 * which are sent from the corresponding hardware to the GCE. 245 * Each hardware event signal corresponds to an event ID in the GCE. 246 * The CMDQ driver can use the following event ID definitions to allow 247 * the client driver to use wait and clear APIs provided by CMDQ, enabling 248 * the GCE to execute operations in the instructions for that event ID. 249 * 250 * The event IDs of GCE1 are mainly used by non-display hardware. 251 */ 252 #define CMDQ_EVENT_VENC3_VENC_RESERVED 0 253 #define CMDQ_EVENT_VENC3_VENC_FRAME_DONE 1 254 #define CMDQ_EVENT_VENC3_VENC_PAUSE_DONE 2 255 #define CMDQ_EVENT_VENC3_JPGENC_DONE 3 256 #define CMDQ_EVENT_VENC3_VENC_MB_DONE 4 257 #define CMDQ_EVENT_VENC3_VENC_128BYTE_DONE 5 258 #define CMDQ_EVENT_VENC3_JPGDEC_DONE 6 259 #define CMDQ_EVENT_VENC3_JPGDEC_C1_DONE 7 260 #define CMDQ_EVENT_VENC3_JPGDEC_INSUFF_DONE 8 261 #define CMDQ_EVENT_VENC3_JPGDEC_C1_INSUFF_DONE 9 262 #define CMDQ_EVENT_VENC3_WP_2ND_STAGE_DONE 10 263 #define CMDQ_EVENT_VENC3_WP_3RD_STAGE_DONE 11 264 #define CMDQ_EVENT_VENC3_PPS_HEADER_DONE 12 265 #define CMDQ_EVENT_VENC3_SPS_HEADER_DONE 13 266 #define CMDQ_EVENT_VENC3_VPS_HEADER_DONE 14 267 #define CMDQ_EVENT_VENC3_VENC_SLICE_DONE 15 268 #define CMDQ_EVENT_VENC3_VENC_SOC_SLICE_DONE 16 269 #define CMDQ_EVENT_VENC3_VENC_SOC_FRAME_DONE 17 270 271 #define CMDQ_EVENT_VENC2_VENC_FRAME_DONE 33 272 #define CMDQ_EVENT_VENC2_VENC_PAUSE_DONE 34 273 #define CMDQ_EVENT_VENC2_JPGENC_DONE 35 274 #define CMDQ_EVENT_VENC2_VENC_MB_DONE 36 275 #define CMDQ_EVENT_VENC2_VENC_128BYTE_DONE 37 276 #define CMDQ_EVENT_VENC2_JPGDEC_DONE 38 277 #define CMDQ_EVENT_VENC2_JPGDEC_C1_DONE 39 278 #define CMDQ_EVENT_VENC2_JPGDEC_INSUFF_DONE 40 279 #define CMDQ_EVENT_VENC2_JPGDEC_C1_INSUFF_DONE 41 280 #define CMDQ_EVENT_VENC2_WP_2ND_STAGE_DONE 42 281 #define CMDQ_EVENT_VENC2_WP_3RD_STAGE_DONE 43 282 #define CMDQ_EVENT_VENC2_PPS_HEADER_DONE 44 283 #define CMDQ_EVENT_VENC2_SPS_HEADER_DONE 45 284 #define CMDQ_EVENT_VENC2_VPS_HEADER_DONE 46 285 #define CMDQ_EVENT_VENC2_VENC_SLICE_DONE 47 286 #define CMDQ_EVENT_VENC2_VENC_SOC_SLICE_DONE 48 287 #define CMDQ_EVENT_VENC2_VENC_SOC_FRAME_DONE 49 288 289 #define CMDQ_EVENT_VENC1_VENC_FRAME_DONE 65 290 #define CMDQ_EVENT_VENC1_VENC_PAUSE_DONE 66 291 #define CMDQ_EVENT_VENC1_JPGENC_DONE 67 292 #define CMDQ_EVENT_VENC1_VENC_MB_DONE 68 293 #define CMDQ_EVENT_VENC1_VENC_128BYTE_DONE 69 294 #define CMDQ_EVENT_VENC1_JPGDEC_DONE 70 295 #define CMDQ_EVENT_VENC1_JPGDEC_C1_DONE 71 296 #define CMDQ_EVENT_VENC1_JPGDEC_INSUFF_DONE 72 297 #define CMDQ_EVENT_VENC1_JPGDEC_C1_INSUFF_DONE 73 298 #define CMDQ_EVENT_VENC1_WP_2ND_STAGE_DONE 74 299 #define CMDQ_EVENT_VENC1_WP_3RD_STAGE_DONE 75 300 #define CMDQ_EVENT_VENC1_PPS_HEADER_DONE 76 301 #define CMDQ_EVENT_VENC1_SPS_HEADER_DONE 77 302 #define CMDQ_EVENT_VENC1_VPS_HEADER_DONE 78 303 #define CMDQ_EVENT_VENC1_VENC_SLICE_DONE 79 304 #define CMDQ_EVENT_VENC1_VENC_SOC_SLICE_DONE 80 305 #define CMDQ_EVENT_VENC1_VENC_SOC_FRAME_DONE 81 306 307 #define CMDQ_EVENT_VDEC1_VDEC_LINE_CNT_INT 192 308 #define CMDQ_EVENT_VDEC1_VDEC_INT 193 309 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_2 194 310 #define CMDQ_EVENT_VDEC1_VDEC_DEC_ERR 195 311 #define CMDQ_EVENT_VDEC1_VDEC_BUSY_OVERFLOW 196 312 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_5 197 313 #define CMDQ_EVENT_VDEC1_VDEC_INI_FETCH_RDY 198 314 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_7 199 315 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_8 200 316 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_9 201 317 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_10 202 318 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_11 203 319 320 #define CMDQ_EVENT_VDEC1_VDEC_GCE_CNT_OP_THR 207 321 322 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_32 224 323 #define CMDQ_EVENT_VDEC1_VDEC_LAT_INT 225 324 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_34 226 325 #define CMDQ_EVENT_VDEC1_VDEC_LAT_DEC_ERR 227 326 #define CMDQ_EVENT_VDEC1_VDEC_LAT_BUSY_OVERFLOW 228 327 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_37 229 328 #define CMDQ_EVENT_VDEC1_VDEC_LAT_INI_FETCH_RDY 230 329 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_39 231 330 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_40 232 331 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_41 233 332 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_42 234 333 #define CMDQ_EVENT_VDEC1_VDEC1_EVENT_43 235 334 335 #define CMDQ_EVENT_VDEC1_VDEC_LAT_GCE_CNT_OP_THR 239 336 337 #define CMDQ_EVENT_IMG_IMG_EVENT_0 256 338 /* CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 ~ 5: 257 ~ 262 */ 339 #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0(n) (257 + (n)) 340 #define CMDQ_EVENT_IMG_TRAW0_DMA_ERR_EVENT 263 341 #define CMDQ_EVENT_IMG_TRAW0_DUMMY_0 264 342 /* CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 ~ 5: 265 ~ 270 */ 343 #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0(n) (265 + (n)) 344 #define CMDQ_EVENT_IMG_TRAW1_DMA_ERR_EVENT 271 345 #define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT 272 346 #define CMDQ_EVENT_IMG_ADLWR0_TILE_DONE_EVENT 273 347 #define CMDQ_EVENT_IMG_ADLWR1_TILE_DONE_EVENT 274 348 #define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 275 349 #define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE 276 350 /* CMDQ_EVENT_IMG_QOF_ACK_EVENT0 ~ 19: 277 ~ 296 */ 351 #define CMDQ_EVENT_IMG_QOF_ACK_EVENT(n) (277 + (n)) 352 /* CMDQ_EVENT_IMG_QOF_ON_EVENT0 ~ 4: 297 ~ 301 */ 353 #define CMDQ_EVENT_IMG_QOF_ON_EVENT(n) (297 + (n)) 354 /* CMDQ_EVENT_IMG_QOF_OFF_EVENT0 ~ 4: 302 ~ 306 */ 355 #define CMDQ_EVENT_IMG_QOF_OFF_EVENT(n) (302 + (n)) 356 /* CMDQ_EVENT_IMG_QOF_SAVE_EVENT0 ~ 4: 307 ~ 311 */ 357 #define CMDQ_EVENT_IMG_QOF_SAVE_EVENT(n) (307 + (n)) 358 /* CMDQ_EVENT_IMG_QOF_RESTORE_EVENT0 ~ 4: 312 ~ 316 */ 359 #define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT(n) (312 + (n)) 360 /* CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P20~5: 317 ~ 322 */ 361 #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2(n) (317 + (n)) 362 #define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT 323 363 #define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT 324 364 #define CMDQ_EVENT_IMG_DIP_DUMMY_0 325 365 #define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 326 366 #define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 327 367 /* CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P20 ~ 5: 328 ~ 333 */ 368 #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2(n) (328 + (n)) 369 /* CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P20 ~ 5: 334 ~ 339 */ 370 #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2(n) (334 + (n)) 371 #define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT 340 372 /* CMDQ_EVENT_IMG_WPE0_DUMMY0~2: 341 ~ 343 */ 373 #define CMDQ_EVENT_IMG_WPE0_DUMMY(n) (341 + (n)) 374 #define CMDQ_EVENT_IMG_OMC_TNR_GCE_FRAME_DONE 344 375 #define CMDQ_EVENT_IMG_OMC_TNR_DONE_SYNC_OUT 345 376 /* CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P20 ~ 5: 346 ~ 351 */ 377 #define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2(n) (346 + (n)) 378 /* CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P20 ~ 5: 352 ~ 357 */ 379 #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2(n) (352 + (n)) 380 #define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT 358 381 /* CMDQ_EVENT_IMG_WPE1_DUMMY0 ~ 2: 359 ~ 361 */ 382 #define CMDQ_EVENT_IMG_WPE1_DUMMY(n) (359 + (n)) 383 #define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 362 384 #define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 363 385 /* CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P20 ~ 5: 364 ~ 369 */ 386 #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2(n) (364 + (n)) 387 #define CMDQ_EVENT_IMG_OMC_LITE_GCE_FRAME_DONE 370 388 #define CMDQ_EVENT_IMG_OMC_LITE_DONE_SYNC_OUT 371 389 /* CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P20 ~ 5: 372 ~ 377 */ 390 #define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2(n) (372 + (n)) 391 /* CMDQ_EVENT_IMG_WPE2_DUMMY0 ~ 2: 378 ~ 380 */ 392 #define CMDQ_EVENT_IMG_WPE2_DUMMY(n) (378 + (n)) 393 #define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE 381 394 #define CMDQ_EVENT_IMG_IMG_EVENT_126 382 395 #define CMDQ_EVENT_IMG_IMG_EVENT_127 383 396 #define CMDQ_EVENT_CAM_CAM_EVENT_0 384 397 #define CMDQ_EVENT_CAM_CAM_SUBA_SW_PASS1_DONE 385 398 #define CMDQ_EVENT_CAM_CAM_SUBB_SW_PASS1_DONE 386 399 #define CMDQ_EVENT_CAM_CAM_SUBC_SW_PASS1_DONE 387 400 #define CMDQ_EVENT_CAM_CAM_SUBA_TFMR_PASS1_DONE 388 401 #define CMDQ_EVENT_CAM_CAM_SUBB_TFMR_PASS1_DONE 389 402 #define CMDQ_EVENT_CAM_CAM_SUBC_TFMR_PASS1_DONE 390 403 /* CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE0 ~ 3: 391 ~ 394 */ 404 #define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE(n) (391 + (n)) 405 /* CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE0 ~ 3: 395 ~ 398 */ 406 #define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE(n) (395 + (n)) 407 /* CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE0 ~ 3: 399 + 402 */ 408 #define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE(n) (399 + (n)) 409 /* CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE0 ~ 3: 403 ~ 406 */ 410 #define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE(n) (403 + (n)) 411 /* CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE0 ~ 3: 407 ~ 409 */ 412 #define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE(n) (407 + (n)) 413 /* CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE0 ~ 3: 411 ~ 413 */ 414 #define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE(n) (411 + (n)) 415 #define CMDQ_EVENT_CAM_MRAW0_SW_PASS1_DONE 415 416 #define CMDQ_EVENT_CAM_MRAW1_SW_PASS1_DONE 416 417 #define CMDQ_EVENT_CAM_MRAW2_SW_PASS1_DONE 417 418 #define CMDQ_EVENT_CAM_MRAW3_SW_PASS1_DONE 418 419 #define CMDQ_EVENT_CAM_UISP_SW_PASS1_DONE 419 420 #define CMDQ_EVENT_CAM_TG_MRAW0_OUT_SOF 420 421 #define CMDQ_EVENT_CAM_TG_MRAW1_OUT_SOF 421 422 #define CMDQ_EVENT_CAM_TG_MRAW2_OUT_SOF 422 423 #define CMDQ_EVENT_CAM_TG_MRAW3_OUT_SOF 423 424 #define CMDQ_EVENT_CAM_PDA0_IRQO_EVENT_DONE_D1 424 425 #define CMDQ_EVENT_CAM_PDA1_IRQO_EVENT_DONE_D1 425 426 #define CMDQ_EVENT_CAM_DPE_DVP_CMQ_EVENT 426 427 #define CMDQ_EVENT_CAM_DPE_DVS_CMQ_EVENT 427 428 #define CMDQ_EVENT_CAM_DPE_DVFG_CMQ_EVENT 428 429 #define CMDQ_EVENT_CAM_CAM_EVENT_45 429 430 #define CMDQ_EVENT_CAM_CAM_EVENT_46 430 431 #define CMDQ_EVENT_CAM_CAM_EVENT_47 431 432 #define CMDQ_EVENT_CAM_CAM_EVENT_48 432 433 /* CMDQ_EVENT_CAM_CAM_SUBA_TG_INT1 ~ 4: 433 ~ 436 */ 434 #define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT(n) (433 + (n) - 1) 435 /* CMDQ_EVENT_CAM_CAM_SUBB_TG_INT1 ~ 4: 437 ~ 440 */ 436 #define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT(n) (437 + (n) - 1) 437 /* CMDQ_EVENT_CAM_CAM_SUBC_TG_INT1 ~ 4: 441 ~ 444 */ 438 #define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT(n) (441 + (n) - 1) 439 #define CMDQ_EVENT_CAM_RAW_O_SOF_SUBA 445 440 #define CMDQ_EVENT_CAM_RAW_O_SOF_SUBB 446 441 #define CMDQ_EVENT_CAM_RAW_O_SOF_SUBC 447 442 #define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBA 448 443 #define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBB 449 444 #define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBC 450 445 #define CMDQ_EVENT_CAM_RAW_SEL_SOF_UISP 451 446 #define CMDQ_EVENT_CAM_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 452 447 #define CMDQ_EVENT_CAM_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 453 448 #define CMDQ_EVENT_CAM_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 454 449 #define CMDQ_EVENT_CAM_CAM_EVENT_71 455 450 #define CMDQ_EVENT_CAM_ADL_WR_FRAME_DONE 456 451 #define CMDQ_EVENT_CAM_ADL_RD_FRAME_DONE 457 452 #define CMDQ_EVENT_CAM_QOF_RAWA_POWER_ON_EVENT 458 453 #define CMDQ_EVENT_CAM_QOF_RAWB_POWER_ON_EVENT 459 454 #define CMDQ_EVENT_CAM_QOF_RAWC_POWER_ON_EVENT 460 455 #define CMDQ_EVENT_CAM_QOF_RAWA_POWER_OFF_EVENT 461 456 #define CMDQ_EVENT_CAM_QOF_RAWB_POWER_OFF_EVENT 462 457 #define CMDQ_EVENT_CAM_QOF_RAWC_POWER_OFF_EVENT 463 458 #define CMDQ_EVENT_CAM_QOF_RAWA_SAVE_EVENT 464 459 #define CMDQ_EVENT_CAM_QOF_RAWB_SAVE_EVENT 465 460 #define CMDQ_EVENT_CAM_QOF_RAWC_SAVE_EVENT 466 461 #define CMDQ_EVENT_CAM_QOF_RAWA_RESTORE_EVENT 467 462 #define CMDQ_EVENT_CAM_QOF_RAWB_RESTORE_EVENT 468 463 #define CMDQ_EVENT_CAM_QOF_RAWC_RESTORE_EVENT 469 464 /* CMDQ_EVENT_CAM_QOF_CAM_EVENT0 ~ 11: 470 ~ 481 */ 465 #define CMDQ_EVENT_CAM_QOF_CAM_EVENT(n) (470 + (n)) 466 /* CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT0 ~ 11: 482 ~ 495 */ 467 #define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT(n) (482 + (n)) 468 #define CMDQ_EVENT_CAM_CCU0_TO_GCE_NON_SEC_IRQ 496 469 #define CMDQ_EVENT_CAM_CCU0_TO_GCE_SEC_IRQ 497 470 #define CMDQ_EVENT_CAM_CCU0_TO_GCE_VM_IRQ 498 471 #define CMDQ_EVENT_CAM_CCU0_TO_GCE_EXCH_VM_IRQ 499 472 #define CMDQ_EVENT_CAM_CCU1_TO_GCE_NON_SEC_IRQ 500 473 #define CMDQ_EVENT_CAM_CCU1_TO_GCE_SEC_IRQ 501 474 #define CMDQ_EVENT_CAM_CCU1_TO_GCE_VM_IRQ 502 475 #define CMDQ_EVENT_CAM_CCU1_TO_GCE_EXCH_VM_IRQ 503 476 /* CMDQ_EVENT_CAM_I2C_CH2_EVENT0 ~ 4: 504 ~ 509 */ 477 #define CMDQ_EVENT_CAM_I2C_CH2_EVENT(n) (504 + (n)) 478 #define CMDQ_EVENT_CAM_CAM_EVENT_125 509 479 #define CMDQ_EVENT_CAM_CAM_EVENT_126 510 480 #define CMDQ_EVENT_CAM_CAM_EVENT_127 511 481 482 #define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MMSRAM_COMM_SMIASSER 898 483 #define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MDP_COMM_SMIASSER 899 484 #define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_DISP_COMM_SMIASSER 900 485 486 /* 487 * GCE Software Tokens 488 * Apart from the event IDs that are already bound to hardware event signals, 489 * the remaining event IDs can be used as software tokens. 490 * This allows the client driver to name and operate them independently, 491 * and their usage is the same as that of hardware events. 492 */ 493 /* Begin of GCE0 software token */ 494 /* Config thread notify trigger thread */ 495 #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 496 /* Trigger thread notify config thread */ 497 #define CMDQ_SYNC_TOKEN_STREAM_EOF 641 498 /* Block Trigger thread until the ESD check finishes */ 499 #define CMDQ_SYNC_TOKEN_ESD_EOF 642 500 #define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 501 /* Check CABC setup finish */ 502 #define CMDQ_SYNC_TOKEN_CABC_EOF 644 503 /* VFP period token for Msync */ 504 #define CMDQ_SYNC_TOKEN_VFP_PERIOD 645 505 /* Software sync token for dual display */ 506 #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1 694 507 #define CMDQ_SYNC_TOKEN_STREAM_EOF_1 695 508 #define CMDQ_SYNC_TOKEN_ESD_EOF_1 696 509 #define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1 697 510 #define CMDQ_SYNC_TOKEN_CABC_EOF_1 698 511 512 /* 513 * GPR access tokens (for HW register backup) 514 * There are 15 32-bit GPR, form 3 GPR as a set 515 * (64-bit for address, 32-bit for value) 516 * 517 * CMDQ_SYNC_TOKEN_GPR_SET0 ~ 4: 700 ~ 704 518 */ 519 #define CMDQ_SYNC_TOKEN_GPR_SET(n) (700 + (n)) 520 #define CMDQ_SYNC_TOKEN_TE_0 705 521 #define CMDQ_SYNC_TOKEN_PREFETCH_TE_0 706 522 #define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON 707 523 #define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE 708 524 525 /* Resource lock event to control resource in GCE thread */ 526 #define CMDQ_SYNC_RESOURCE_WROT0 710 527 #define CMDQ_SYNC_RESOURCE_WROT1 711 528 /* Hardware TRACE software token */ 529 #define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT 712 530 #define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK 713 531 /* Software sync token for dual display */ 532 #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3 714 533 #define CMDQ_SYNC_TOKEN_STREAM_EOF_3 715 534 #define CMDQ_SYNC_TOKEN_ESD_EOF_3 716 535 #define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3 717 536 #define CMDQ_SYNC_TOKEN_CABC_EOF_3 718 537 /* End of GCE0 software token */ 538 539 /* Begin of GCE1 software token */ 540 /* CMDQ_SYNC_TOKEN_IMGSYS_POOL0 ~ 300: 512 ~ 812 */ 541 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL(n) (512 + (n)) 542 /* ISP software token */ 543 #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 813 544 #define CMDQ_SYNC_TOKEN_IMGSYS_OMC_TNR 814 545 #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 815 546 #define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 816 547 #define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 817 548 #define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 818 549 #define CMDQ_SYNC_TOKEN_IMGSYS_DIP 819 550 #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 820 551 #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 821 552 #define CMDQ_SYNC_TOKEN_IPESYS_ME 822 553 #define CMDQ_SYNC_TOKEN_APUSYS_APU 823 554 #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 824 555 #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 825 556 #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 826 557 #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 827 558 #define CMDQ_SYNC_TOKEN_IMGSYS_OMC_LITE 828 559 /* IMG software token for QoS */ 560 #define CMDQ_SYNC_TOKEN_IMGSYS_QOS_LOCK 829 561 /* IMG software token for Qof */ 562 #define CMDQ_SYNC_TOKEN_DIP_POWER_CTRL 830 563 #define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_ON 831 564 #define CMDQ_SYNC_TOKEN_DIP_PWR_ON 832 565 #define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_OFF 833 566 #define CMDQ_SYNC_TOKEN_DIP_PWR_OFF 834 567 #define CMDQ_SYNC_TOKEN_DIP_PWR_HAND_SHAKE 835 568 #define CMDQ_SYNC_TOKEN_TRAW_POWER_CTRL 836 569 #define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_ON 837 570 #define CMDQ_SYNC_TOKEN_TRAW_PWR_ON 838 571 #define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_OFF 839 572 #define CMDQ_SYNC_TOKEN_TRAW_PWR_OFF 840 573 #define CMDQ_SYNC_TOKEN_TRAW_PWR_HAND_SHAKE 841 574 /* End of GCE1 software token */ 575 576 /* Begin of common software token */ 577 /* 578 * Notify normal CMDQ there are some secure task done 579 * MUST NOT CHANGE, this token sync with secure world 580 */ 581 #define CMDQ_SYNC_SECURE_THR_EOF 940 582 /* CMDQ use software token */ 583 #define CMDQ_SYNC_TOKEN_USER_0 941 584 #define CMDQ_SYNC_TOKEN_USER_1 942 585 #define CMDQ_SYNC_TOKEN_POLL_MONITOR 943 586 #define CMDQ_SYNC_TOKEN_TPR_LOCK 942 587 /* TZMP software token */ 588 #define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 943 589 #define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 944 590 #define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 945 591 #define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 946 592 #define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 947 593 #define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 948 594 #define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT 949 595 #define CMDQ_SYNC_TOKEN_TZMP_ADL_SET 950 596 /* PREBUILT software token */ 597 #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 951 598 #define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 952 599 #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 953 600 #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 954 601 #define CMDQ_SYNC_TOKEN_DISP_VA_START 955 602 #define CMDQ_SYNC_TOKEN_DISP_VA_END 956 603 604 /* 605 * Event for GPR timer, used in sleep and poll with timeout 606 * 607 * CMDQ_TOKEN_GPR_TIMER_R0~15: 994 ~ 1009 608 */ 609 #define CMDQ_TOKEN_GPR_TIMER_R(n) (994 + (n)) 610 /* End of common software token */ 611 612 #endif 613