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/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST Microelectronics SPEAr SPI CS GPIO Controller
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
[all …]
/linux/drivers/clocksource/
H A Dtimer-nxp-stm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2018,2021-2025 NXP
9 * timing functions. STM includes a 32-bit count-up timer and four
10 * 32-bit compare channels with a separate interrupt source for each
12 * 8-bit prescale value (1 to 256). It has ability to stop the timer
27 #define STM_CR_TEN BIT(0)
28 #define STM_CR_FRZ BIT(1)
39 #define STM_CCR_CEN BIT(0)
46 #define STM_CIR_CIF BIT(0)
61 struct clocksource cs; member
[all …]
H A Dtimer-pistachio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pistachio clocksource based on general-purpose timers
27 #define TIMER_ME_GLOBAL BIT(0)
32 #define TIMER_ME_LOCAL BIT(0)
48 struct clocksource cs; member
53 #define to_pistachio_clocksource(cs) \ argument
54 container_of(cs, struct pistachio_clocksource, cs)
61 static inline void gpt_writel(void __iomem *base, u32 value, u32 offset, in gpt_writel() argument
64 writel(value, base + 0x20 * gpt_id + offset); in gpt_writel()
68 pistachio_clocksource_read_cycles(struct clocksource *cs) in pistachio_clocksource_read_cycles() argument
[all …]
H A Dsh_cmt.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
51 * infers the start/stop bit position in the control register and the channel
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
56 * in the documentation but using start/stop bit 5 and having its registers
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
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H A Dtimer-microchip-pit64b.c1 // SPDX-License-Identifier: GPL-2.0
3 * 64-bit Periodic Interval Timer driver
20 #define MCHP_PIT64B_CR_START BIT(0)
21 #define MCHP_PIT64B_CR_SWRST BIT(8)
24 #define MCHP_PIT64B_MR_CONT BIT(0)
26 #define MCHP_PIT64B_MR_SGCLK BIT(3)
34 #define MCHP_PIT64B_IER_PERIOD BIT(0)
51 * struct mchp_pit64b_timer - PIT64B timer data structure
55 * @mode: precomputed value for mode register
65 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
[all …]
H A Dtimer-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2025 NVIDIA Corporation. All rights reserved.
27 #define TMRCR_ENABLE BIT(31)
28 #define TMRCR_PERIODIC BIT(30)
32 #define TMRSR_INTR_CLR BIT(30)
40 #define WDTCR_SYSTEM_POR_RESET_ENABLE BIT(16)
41 #define WDTCR_SYSTEM_DEBUG_RESET_ENABLE BIT(15)
42 #define WDTCR_REMOTE_INT_ENABLE BIT(14)
43 #define WDTCR_LOCAL_FIQ_ENABLE BIT(13)
44 #define WDTCR_LOCAL_INT_ENABLE BIT(12)
[all …]
H A Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
59 unsigned long value) in em_sti_write() argument
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
95 clk_disable(p->clk); in em_sti_disable()
103 /* the STI hardware buffers the 48-bit count, but to in em_sti_count()
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/linux/drivers/gpu/drm/i915/gt/
H A Dgen8_engine_cs.h1 /* SPDX-License-Identifier: MIT */
43 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
44 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
46 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
47 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
48 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
50 u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs);
79 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1) in __gen8_emit_write_rcs() argument
81 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_write_rcs()
82 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE; in __gen8_emit_write_rcs()
[all …]
/linux/drivers/edac/
H A Damd64_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * cleared to prevent re-enabling the hardware by this driver.
21 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
33 /* Per-node stuff */
41 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
42 * or higher value'.
47 u32 scrubval; /* bit pattern for scrub rate */
83 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
96 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
108 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg); in f15h_select_dct()
[all …]
/linux/drivers/gpio/
H A Dgpio-spear-spics.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
31 * struct spear_spics - represents spi chip select control
34 * @sw_enable_bit: bit to enable s/w control over chipselects
35 * @cs_value_bit: bit to program high or low chipselect
37 * @cs_enable_shift: bit pos of cs_enable_mask
38 * @use_count: use count of a spi controller cs lines
55 int value) in spics_set_value() argument
61 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
62 if (spics->last_off != offset) { in spics_set_value()
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/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
81 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
85 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
86 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
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H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
35 #define FMC2_BCR1_CCLKEN BIT(20)
36 #define FMC2_BCR1_FMC2EN BIT(31)
39 #define FMC2_BCR_MBKEN BIT(0)
40 #define FMC2_BCR_MUXEN BIT(1)
43 #define FMC2_BCR_FACCEN BIT(6)
44 #define FMC2_BCR_BURSTEN BIT(8)
45 #define FMC2_BCR_WAITPOL BIT(9)
46 #define FMC2_BCR_WAITCFG BIT(11)
47 #define FMC2_BCR_WREN BIT(12)
[all …]
/linux/include/uapi/drm/
H A Dhabanalabs_accel.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2023 HabanaLabs, Ltd.
14 * Defines that are asic-specific but constitutes as ABI between kernel driver
195 * stream id is a running number from 0 up to (N-1), where N is the number
656 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
683 * enum hl_device_status - Device status information.
715 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
717 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
718 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
719 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
[all …]
/linux/drivers/i2c/busses/
H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
35 /* I2C register bit definitions */
36 #define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
37 #define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address
38 #define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave
39 #define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
40 #define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit
41 #define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost
42 #define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond.
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/linux/arch/x86/realmode/rm/
H A Dtrampoline_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
7 * 15 Sept 2005 Eric Biederman: 64bit PIC support
9 * Entry: CS:IP point to the start of our code, we are
15 * with 16-bit addressing and 16-bit data. CS has some value
20 * now enter a 64bit kernel that lives at arbitrary 64bit
24 * --full-contents --reloc to make sure there are no relocation
33 #include <asm/processor-flags.h>
67 mov %cs, %ax # Code and data in the same place
82 * operand size is 16bit. Use lgdtl instead to force operand size
83 * to 32 bit.
[all …]
H A Dtrampoline_32.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Entry: CS:IP point to the start of our code, we are
18 * with 16-bit addressing and 16-bit data. CS has some value
19 * and IP is zero. Thus, we load CS to the physical segment
33 wbinvd # Needed for NUMA-Q should be harmless for others
37 mov %cs, %ax # Code and data in the same place
47 * operand size is 16bit. Use lgdtl instead to force operand size
48 * to 32 bit.
53 movw $1, %dx # protected mode (PE) bit
/linux/drivers/spi/
H A Dspi-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
19 #include <linux/dma-mapping.h>
44 /* Bitfields in CS */
76 #define DRV_NAME "spi-bcm2835"
85 * struct bcm2835_spi - BCM2835 SPI controller
88 * @cs_gpio: chip-select GPIO descriptor
102 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
116 * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
[all …]
/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit.
28 #define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1)
29 #define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3)
30 #define EBI2_CS2_ENABLE_MASK BIT(4)
31 #define EBI2_CS3_ENABLE_MASK BIT(5)
32 #define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7)
33 #define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9)
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
[all …]
H A Dintel-ixp4xx-eb.c1 // SPDX-License-Identifier: GPL-2.0-only
32 /* Bits inside each CS timing register */
34 #define IXP4XX_EXP_CS_EN BIT(31)
35 #define IXP456_EXP_PAR_EN BIT(30) /* Only on IXP45x and IXP46x */
50 #define IXP4XX_EXP_CNFG_0 BIT(9) /* Always zero */
51 #define IXP43X_EXP_SYNC_INTEL BIT(8) /* Only on IXP43x */
52 #define IXP43X_EXP_EXP_CHIP BIT(7) /* Only on IXP43x, dangerous to touch on IXP42x */
53 #define IXP4XX_EXP_BYTE_RD16 BIT(6)
54 #define IXP4XX_EXP_HRDY_POL BIT(5) /* Only on IXP42x */
55 #define IXP4XX_EXP_MUX_EN BIT(4)
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/linux/drivers/mtd/nand/raw/
H A Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank)
21 #define TRANSFER_SPARE_REG__FLAG BIT(0)
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
39 #define MULTIPLANE_OPERATION__FLAG BIT(0)
42 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
45 #define COPYBACK_DISABLE__FLAG BIT(0)
48 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
51 #define CACHE_READ_ENABLE__FLAG BIT(0)
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H A Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
28 * correct line. For example when the bit (1 << 2) is set in the address
31 #define NAND_CMD_ALE BIT(2) /* address latch enable */
32 #define NAND_CMD_CLE BIT(3) /* command latch enable */
33 #define NAND_CMD_CS BIT(4) /* chip select */
34 #define NAND_CMD_SE BIT(5) /* spare area access latch */
35 #define NAND_CMD_WP BIT(6) /* write protect */
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/linux/arch/x86/kernel/
H A Dptrace.c1 // SPDX-License-Identifier: GPL-2.0-only
111 REG_OFFSET_NAME(cs),
119 * regs_query_register_offset() - query register offset from its name
123 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
128 for (roff = regoffset_table; roff->name != NULL; roff++) in regs_query_register_offset()
129 if (!strcmp(roff->name, name)) in regs_query_register_offset()
130 return roff->offset; in regs_query_register_offset()
131 return -EINVAL; in regs_query_register_offset()
135 * regs_query_register_name() - query register name from its offset
144 for (roff = regoffset_table; roff->name != NULL; roff++) in regs_query_register_name()
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/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static void clocksource_enqueue(struct clocksource *cs);
25 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
27 u64 delta = clocksource_delta(end, start, cs->mask, cs->max_raw_delt in cycles_to_nsec_safe()
195 clocksource_change_rating(struct clocksource * cs,int rating) clocksource_change_rating() argument
202 __clocksource_unstable(struct clocksource * cs) __clocksource_unstable() argument
231 clocksource_mark_unstable(struct clocksource * cs) clocksource_mark_unstable() argument
253 cs_watchdog_read(struct clocksource * cs,u64 * csnow,u64 * wdnow) cs_watchdog_read() argument
357 struct clocksource *cs = (struct clocksource *)csin; clocksource_verify_one_cpu() local
362 clocksource_verify_percpu(struct clocksource * cs) clocksource_verify_percpu() argument
421 struct clocksource *cs; clocksource_reset_watchdog() local
433 struct clocksource *cs; clocksource_watchdog() local
627 clocksource_enqueue_watchdog(struct clocksource * cs) clocksource_enqueue_watchdog() argument
644 struct clocksource *cs, *old_wd; clocksource_select_watchdog() local
679 clocksource_dequeue_watchdog(struct clocksource * cs) clocksource_dequeue_watchdog() argument
693 struct clocksource *cs, *tmp; __clocksource_watchdog_kthread() local
731 clocksource_is_watchdog(struct clocksource * cs) clocksource_is_watchdog() argument
738 clocksource_enqueue_watchdog(struct clocksource * cs) clocksource_enqueue_watchdog() argument
745 clocksource_dequeue_watchdog(struct clocksource * cs) clocksource_dequeue_watchdog() argument
748 clocksource_is_watchdog(struct clocksource * cs) clocksource_is_watchdog() argument
749 clocksource_mark_unstable(struct clocksource * cs) clocksource_mark_unstable() argument
756 clocksource_is_suspend(struct clocksource * cs) clocksource_is_suspend() argument
761 __clocksource_suspend_select(struct clocksource * cs) __clocksource_suspend_select() argument
790 struct clocksource *cs, *old_suspend; clocksource_suspend_select() local
818 clocksource_start_suspend_timing(struct clocksource * cs,u64 start_cycles) clocksource_start_suspend_timing() argument
856 clocksource_stop_suspend_timing(struct clocksource * cs,u64 cycle_now) clocksource_stop_suspend_timing() argument
891 struct clocksource *cs; clocksource_suspend() local
903 struct clocksource *cs; clocksource_resume() local
929 clocksource_max_adjustment(struct clocksource * cs) clocksource_max_adjustment() argument
990 clocksource_update_max_deferment(struct clocksource * cs) clocksource_update_max_deferment() argument
1008 struct clocksource *cs; clocksource_find_best() local
1031 struct clocksource *best, *cs; __clocksource_select() local
1122 clocksource_enqueue(struct clocksource * cs) clocksource_enqueue() argument
1148 __clocksource_update_freq_scale(struct clocksource * cs,u32 scale,u32 freq) __clocksource_update_freq_scale() argument
1240 __clocksource_register_scale(struct clocksource * cs,u32 scale,u32 freq) __clocksource_register_scale() argument
1277 clocksource_unbind(struct clocksource * cs) clocksource_unbind() argument
1316 clocksource_unregister(struct clocksource * cs) clocksource_unregister() argument
1408 struct clocksource *cs; unbind_clocksource_store() local
[all...]
/linux/include/linux/
H A Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
40 * @read: Returns a cycle value, passes clocksource as argument
42 * subtraction of non 64 bit counters
46 * @maxadj: Maximum adjustment value to mult (~11%)
49 * @archdata: Optional arch-specific data
50 * @max_cycles: Maximum safe cycle value which won't overflow on
52 * @max_raw_delta: Maximum safe delta value for negative motion detection
56 * @rating: Rating value for selection (higher is better)
[all …]
/linux/Documentation/input/devices/
H A Diforce-protocol.rst7 Home page at `<http://web.archive.org/web/*/http://www.esil.univ-mrs.fr>`_
16 specify force effects to I-Force 2.0 devices. None of this information comes
25 send data to your I-Force device based on what you read in this document.
30 All values are hexadecimal with big-endian encoding (msb on the left). Beware,
31 values inside packets are encoded using little-endian. Bytes whose roles are
35 ------------------------
40 2B OP LEN DATA CS
43 CS is the checksum. It is equal to the exclusive or of all bytes.
51 The 2B, LEN and CS fields have disappeared, probably because USB handles
59 This packet is used to indicate the state of each button and the value of each
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